Martin L. Schmatz
According to our database1,
Martin L. Schmatz
authored at least 32 papers
between 2004 and 2023.
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Bibliography
2023
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2023
2016
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Conference on Cloud Engineering Workshop, 2016
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016
2015
When Virtual Meets Physical at the Edge: A Field Study on Datacenters' Virtual Traffic.
Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2015
Proceedings of the 35th IEEE International Conference on Distributed Computing Systems, 2015
2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation.
Proceedings of the IEEE International Conference on Acoustics, 2014
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm<sup>2</sup> in 32 nm SOI CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS.
IEEE J. Solid State Circuits, 2013
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2010
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS.
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2009
2008
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth.
IEEE J. Solid State Circuits, 2008
A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the ESSCIRC 2008, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Low-Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components.
IEEE Trans. Commun., 2006
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
A 0.94-ps-RMS-jitter 0.016-mm<sup>2</sup> 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links.
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
2004
IEEE J. Solid State Circuits, 2004
Proceedings of the Telecommunications and Networking, 2004