An algorithm for optimal two-dimensional compaction of VLSI layouts. - Martine D. F. Schlag; Yuh-Zen Liao; C. K. Wong (Integr., 1983)

Maximizing pin alignment by pin permutations. - Martine D. F. Schlag; Lin S. Woo; Chak-Kuen Wong (Integr., 1984)

vFP: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms. - Dorab Patel; Martine D. F. Schlag; Milos D. Ercegovac (FPCA, 1985)

A Method for Improving Cascode-Switch Macro Wirability. - Martine D. F. Schlag; Ellen J. Yoffa; Peter S. Hauge; Chak-Kuen Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

On some union and intersection problems for polygons with fixed orientations. - Peter Widmayer; Ying-Fung Wu; Martine D. F. Schlag; Chak-Kuen Wong (Computing, 1986)

The planar topology of functional programs. - Martine D. F. Schlag (FPCA, 1987)

Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles. - Ying-Fung Wu; Peter Widmayer; Martine D. F. Schlag; C. K. Wong (IEEE Trans. Computers, 1987)

An O(n log n) algorithm for 1-D tile compaction. - Richard Anderson 001; Simon Kahan; Martine D. F. Schlag (ICCAD, 1989)

An O(n log n) Algorithm for 1-D Tile Compaction. - Richard Anderson 001; Simon Kahan; Martine D. F. Schlag (WG, 1989)

Bounds on signal delay in RC mesh networks. - Pak K. Chan; Martine D. F. Schlag (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip. - Pak K. Chan; Martine D. F. Schlag (IEEE Trans. Computers, 1990)

Delay optimization of carry-skip adders and block carry-lookahead adders. - Pak K. Chan; Martine D. F. Schlag; Clark D. Thomborson; Vojin G. Oklobdzija (IEEE Symposium on Computer Arithmetic, 1991)

Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. - Martine D. F. Schlag; Jackson Kong; Pak K. Chan (ICCD, 1992)

Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. - Pak K. Chan; Martine D. F. Schlag; Clark D. Thomborson; Vojin G. Oklobdzija (IEEE Trans. Computers, 1992)

On Routability Prediction for Field-Programmable Gate Arrays. - Pak K. Chan; Martine D. F. Schlag; Jason Y. Zien (DAC, 1993)

Spectral K-Way Ratio-Cut Partitioning and Clustering. - Pak K. Chan; Martine D. F. Schlag; Jason Y. Zien (DAC, 1993)

Single-Layer Cylindrical Compaction. - Richard Anderson 001; Simon Kahan; Martine D. F. Schlag (Algorithmica, 1993)

Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology. - Martine D. F. Schlag; Pak K. Chan; Jackson Kong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Spectral K-way ratio-cut partitioning and clustering. - Pak K. Chan; Martine D. F. Schlag; Jason Y. Zien (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Routability-driven technology mapping for lookup table-based FPGA's. - Martine D. F. Schlag; Jackson Kong; Pak K. Chan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Spectral-Based Multi-Way FPGA Partitioning. - Pak K. Chan; Martine D. F. Schlag; Jason Y. Zien (FPGA, 1995)

Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. - Jason Y. Zien; Martine D. F. Schlag; Pak K. Chan (ICCAD, 1996)

Detection of Multiple Faults in Two-Dimensional ILAs. - Martine D. F. Schlag; F. Joel Ferguson (IEEE Trans. Computers, 1996)

Spectral-based multiway FPGA partitioning. - Pak K. Chan; Martine D. F. Schlag; Jason Y. Zien (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Acceleration of an FPGA router. - Pak K. Chan; Martine D. F. Schlag (FCCM, 1997)

Hybrid spectral/iterative partitioning. - Jason Y. Zien; Pak K. Chan; Martine D. F. Schlag (ICCAD, 1997)

Multilevel spectral hypergraph partitioning with arbitrary vertex sizes. - Jason Y. Zien; Martine D. F. Schlag; Pak K. Chan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

New parallelization and convergence results for NC: a negotiation-based FPGA router. - Pak K. Chan; Martine D. F. Schlag (FPGA, 2000)

Distributed-memory parallel routing for field-programmable gatearrays. - Pak K. Chan; Martine D. F. Schlag; Carl Ebeling; Larry McMurchie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Parallel placement for field-programmable gate arrays. - Pak K. Chan; Martine D. F. Schlag (FPGA, 2003)