Efficient Two-Level Mesh based Simulation of PRAMs. - Martti Forsell; Martti Penttonen; Ville Leppänen (ISPAN, 1996)

Minimal pipeline architecture - an alternative to superscalar architecture. - Martti Forsell (Microprocess. Microsystems, 1996)

MTAC - A Multithreaded VLIW Architecture for PRAM Simulation. - Martti Forsell (J. Univers. Comput. Sci., 1997)

Fast processor core selection for WLAN modem using mappability estimation. - Juha-Pekka Soininen; Jari Kreku; Yang Qu; Martti Forsell (CODES, 2002)

A Network on Chip Architecture and Design Methodology. - Shashi Kumar; Axel Jantsch; Mikael Millberg; Johnny Öberg; Juha-Pekka Soininen; Martti Forsell; Kari Tiensyrjä; Ahmed Hemani (ISVLSI, 2002)

Architectural differences of efficient sequential and parallel computers. - Martti Forsell (J. Syst. Archit., 2002)

A Scalable High-Performance Computing Solution for Networks on Chips. - Martti Forsell (IEEE Micro, 2002)

Context-based compression of binary images in parallel. - Eugene I. Ageenko; Martti Forsell; Pasi Fränti (Softw. Pract. Exp., 2002)

A Parallel Computer as a NOC Region. - Martti Forsell (Networks on Chip, 2003)

Extending Platform-Based Design to Network on Chip Systems. - Juha-Pekka Soininen; Axel Jantsch; Martti Forsell; Antti Pelkonen; Jari Kreku; Shashi Kumar (VLSI Design, 2003)

Designing NOCs with a parallel extension of c. - Martti Forsell (FDL, 2004)

Efficient barrier synchronization mechanism for emulated shared memory NOCs. - Martti Forsell (SoC, 2004)

Ec - a compiler for the e-language [NOC applications]. - Martti Forsell (SoC, 2004)

ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs. - Martti Forsell (SoC, 2005)

Realising constant time parallel algorithms with active memory modules. - Martti Forsell (Int. J. Electron. Bus., 2005)

Reducing the associativity and size of step caches in CRCW operation. - Martti Forsell (IPDPS, 2006)

Realizing Multioperations for Step Cached MP-SOCs. - Martti Forsell (SoC, 2006)

HPPC 2007: Workshop on Highly Parallel Processing on a Chip. - Martti Forsell; Jesper Larsson Träff (Euro-Par Workshops, 2007)

Moving Threads: A Non-Conventional Approach for Mapping Computation to MP-SOC. - Martti Forsell; Ville Leppänen (PDPTA, 2007)

Second Workshop on Highly Parallel Processing on a Chip (HPPC 2008). - Martti Forsell; Jesper Larsson Träff (Euro-Par Workshops, 2008)

Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architectures. - Martti Forsell; Jussi Roivainen (PDPTA, 2008)

Outline of RISC-based core for multiprocessor on chip architecture supporting moving threads. - Jani Paakkulainen; Jari-Matti Mäkelä; Ville Leppänen; Martti Forsell (CompSysTech, 2009)

HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? - Martti Forsell; H. Peter Hofstee; Ahmed Jerraya; Chris R. Jesshope; Uzi Vishkin; Jesper Larsson Träff (Euro-Par Workshops, 2009)

HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip. - Martti Forsell; Jesper Larsson Träff (Euro-Par Workshops, 2009)

Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. - Martti Forsell (NOCS, 2009)

MTPA - A Processor Architecture for MP-SOCs Employing the Moving Threads Paradigm. - Martti Forsell; Ville Leppänen (PDPTA, 2009)

HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chip. - Martti Forsell; Jesper Larsson Träff (Euro-Par Workshops, 2010)

HPPC 2010: 5th Workshop on Highly Parallel Processing on a Chip. - Martti Forsell; Jesper Larsson Träff (Euro-Par Workshops (1), 2010)

Supporting Concurrent Memory Access and Multioperations in Moving Threads CMPs. - Martti Forsell; Ville Leppänen (PDPTA, 2010)

Layouts for Sparse Networks Supporting Throughput Computing. - Ville Leppänen; Martti Penttonen; Martti Forsell (PDPTA, 2010)

On the Performance and Cost of Some PRAM Models on CMP Hardware. - Martti Forsell (Int. J. Found. Comput. Sci., 2010)

A layout for sparse cube-connected-cycles network. - Ville Leppänen; Martti Penttonen; Martti Forsell (CompSysTech, 2011)

RISC-based moving threads multicore architecture. - Jari-Matti Mäkelä; Ville Leppänen; Martti Forsell (CompSysTech, 2011)

Cost of Sparse Mesh Layouts Supporting Throughput Computing. - Martti Forsell; Ville Leppänen; Martti Penttonen (DSD, 2011)

A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads. - Martti Forsell (Int. J. Netw. Comput., 2011)

Performance comparison of some shared memory organizations for 2D mesh-like NOCs. - Martti Forsell (Microprocess. Microsystems, 2011)

A moving threads processor architecture MTPA. - Martti Forsell; Ville Leppänen (J. Supercomput., 2011)

Preliminary analysis of feasible benchmark problems for the hydrid PRAM/NUMA REPLICA architecture. - Jari-Matti Mäkelä; Ville Leppänen; Martti Forsell (CompSysTech, 2012)

Multi-core Portability Abstraction. - Martti Forsell; Mikko Hiivala (IPDPS Workshops, 2012)

Design of the Language Replica for Hybrid PRAM-NUMA Many-core Architectures. - Jari-Matti Mäkelä; Erik Hansson; Daniel Åkesson; Martti Forsell; Christoph W. Kessler; Ville Leppänen (ISPA, 2012)

Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture. - Jari-Matti Mäkelä; Ville Leppänen; Martti Forsell (CompSysTech, 2013)

DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing. - Thomas Canhao Xu; Ville Leppänen; Martti Forsell (DASC, 2013)

Hardware and Software Support for NUMA Computing on Configurable Emulated Shared Memory Architectures. - Martti Forsell; Erik Hansson; Christoph W. Kessler; Jari-Matti Mäkelä; Ville Leppänen (IPDPS Workshops, 2013)

An Extended PRAM-NUMA Model of Computation for TCF Programming. - Martti Forsell; Ville Leppänen (Int. J. Netw. Comput., 2013)

Exploration of a Heterogeneous Concentrated-Sparse On-Chip Interconnect for Energy Efficient Multicore Architecture. - Thomas Canhao Xu; Ville Leppänen; Martti Forsell (CIT, 2014)

REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor. - Martti Forsell; Jussi Roivainen (ACSSC, 2014)

A Quantitative Comparison of PRAM based Emulated Shared Memory Architectures to Current Multicore CPUs and GPUs. - Erik Hansson; Erik Alnervik; Christoph W. Keßler; Martti Forsell (ARCS Workshops, 2014)

Prototyping the MBTAC Processor for the REPLICA CMP. - Martti Forsell; Jussi Roivainen; Ville Leppänen (IPDPS Workshops, 2014)

NUMA Computing with Hardware and Software Co-Support on Configurable Emulated Shared Memory Architectures. - Martti Forsell; Erik Hansson; Christoph W. Kessler; Jari-Matti Mäkelä; Ville Leppänen (Int. J. Netw. Comput., 2014)

Cost of Bandwidth-Optimized Sparse Mesh Layouts. - Martti Forsell; Ville Leppänen; Martti Penttonen (PaCT, 2015)

A study on energy used to deliver H.264/AVC and H.265/HEVC video content. - Mohammadhassan Safavi; Saeed Bastani; Zhi Zhang; Martti Forsell; Olli Mämmelä; Björn Landfeldt (CAMAD, 2016)

Compiler assisted dynamic allocation of finite hardware acceleration resources for parallel tasks. - Jari-Matti Mäkelä; Martti Forsell; Ville Leppänen (CompSysTech, 2016)

The REPLICA on-chip network. - Martti Forsell; Jussi Roivainen; Ville Leppänen (NORCAS, 2016)

Outline of a Thick Control Flow Architecture. - Martti Forsell; Jussi Roivainen; Ville Leppänen (SBAC-PAD (Workshops), 2016)

Towards a Language Framework for Thick Control Flows. - Jari-Matti Mäkelä; Martti Forsell; Ville Leppänen (IPDPS Workshops, 2017)

Supporting concurrent memory access in TCF-aware processor architectures. - Martti Forsell; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (NORCAS, 2017)

Towards Energy-Efficient Adaptive Mpeg-Dash Streaming Using Hevc. - Mikko Uitto; Martti Forsell (ICME Workshops, 2018)

Implementation of Multioperations in Thick Control Flow Processors. - Martti Forsell; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (IPDPS Workshops, 2018)

Supporting concurrent memory access in TCF processor architectures. - Martti Forsell; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (Microprocess. Microsystems, 2018)

REPLICA MBTAC: multithreaded dual-mode processor. - Martti Forsell; Jussi Roivainen; Ville Leppänen (J. Supercomput., 2018)

Reducing Power Consumption in Mobile Terminals - Video Computing Perspective. - Martti Forsell (Greening Video Distribution Networks, 2018)

Optimizing Memory Access in TCF Processors with Compute-Update Operations. - Martti Forsell; Jussi Roivainen; Jesper Larsson Träff (IPDPS Workshops, 2020)

Performance and programmability comparison of the thick control flow architecture and current multicore processors. - Martti Forsell; Sara Nikula; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (J. Supercomput., 2022)

Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors. - Martti Forsell; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (NorCAS, 2023)

Realizing multioperations and multiprefixes in Thick Control Flow processors. - Martti Forsell; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (Microprocess. Microsystems, 2023)