Directional and single-driver wires in FPGA interconnect. - Guy Lemieux; Edmund Lee 002; Marvin Tom; Anthony J. Yu (FPT, 2004)

Logic block clustering of large designs for channel-width constrained FPGAs. - Marvin Tom; Guy G. Lemieux (DAC, 2005)

Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. - Marvin Tom; David Leong; Guy G. Lemieux (ICCAD, 2006)

Clock-Aware FPGA Placement Contest. - Stephen Yang; Chandra Mulpuri; Sainath Reddy; Meghraj Kalase; Srinivasan Dasasathyan; Mehrdad E. Dehkordi; Marvin Tom; Rajat Aggarwal (ISPD, 2017)

ISPD 2020 Physical Mapping of Neural Networks on a Wafer-Scale Deep Learning Accelerator. - Michael James 002; Marvin Tom; Patrick Groeneveld; Vladimir Kibardin (ISPD, 2020)

ISPD 2021 Wafer-Scale Physics Modeling Contest: A New Frontier for Partitioning, Placement and Routing. - Patrick Groeneveld; Michael James 002; Vladimir Kibardin; Ilya Sharapov; Marvin Tom; Leo Wang (ISPD, 2021)

Cerebras-GPT: Open Compute-Optimal Language Models Trained on the Cerebras Wafer-Scale Cluster. - Nolan Dey; Gurpreet Gosal; Zhiming Chen; Hemant Khachane; William Marshall; Ribhu Pathria; Marvin Tom; Joel Hestness (CoRR, 2023)

BTLM-3B-8K: 7B Parameter Performance in a 3B Parameter Model. - Nolan Dey; Daria Soboleva; Faisal Al-Khateeb; Bowen Yang; Ribhu Pathria; Hemant Khachane; Shaheer Muhammad; Zhiming Chen; Robert Myers; Jacob Robert Steeves; Natalia Vassilieva; Marvin Tom; et al. (CoRR, 2023)