High-Throughput VLSI Architecture for Soft-Decision Decoding with ORBGRAND. - Syed Mohsin Abbas; Thibaud Tonnellier; Furkan Ercan; Marwan Jalaleddine; Warren J. Gross (ICASSP, 2021)

High-Throughput VLSI Architecture for GRAND Markov Order. - Syed Mohsin Abbas; Marwan Jalaleddine; Warren J. Gross (SiPS, 2021)

GRAND for Rayleigh Fading Channels. - Syed Mohsin Abbas; Marwan Jalaleddine; Warren J. Gross (GLOBECOM (Workshops), 2022)

High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND. - Syed Mohsin Abbas; Thibaud Tonnellier; Furkan Ercan; Marwan Jalaleddine; Warren J. Gross (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Hardware Architecture for Guessing Random Additive Noise Decoding Markov Order (GRAND-MO). - Syed Mohsin Abbas; Marwan Jalaleddine; Warren J. Gross (J. Signal Process. Syst., 2022)

Step-GRAND: A Low Latency Universal Soft-Input Decoder. - Syed Mohsin Abbas; Chi-Ying Tsui; Marwan Jalaleddine; Warren J. Gross (GLOBECOM (Workshops), 2023)

Partial Ordered Statistics Decoding with Enhanced Error Patterns. - Marwan Jalaleddine; Huayi Zhou 002; Jiajie Li 001; Warren J. Gross (ISIT, 2023)

xSA: A Binary Cross-Entropy Simulated Annealing Polar Decoder. - Ryan Seah; Huayi Zhou 002; Marwan Jalaleddine; Warren J. Gross (ISTC, 2023)

List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding. - Syed Mohsin Abbas; Marwan Jalaleddine; Warren J. Gross (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Decoding of Polar Codes Using Quadratic Unconstrained Binary Optimization. - Huayi Zhou 002; Ryan Seah; Marwan Jalaleddine; Warren J. Gross (IEEE J. Sel. Areas Commun., 2024)

Reduced-Complexity Projection-Aggregation List Decoder for Reed-Muller Codes. - Jiajie Li 001; Huayi Zhou 002; Marwan Jalaleddine; Warren J. Gross (IEEE Trans. Commun., 2025)

Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding. - Syed Mohsin Abbas; Marwan Jalaleddine; Chi-Ying Tsui; Warren J. Gross (IEEE Trans. Very Large Scale Integr. Syst., 2025)