An Empirical Study of On-chip Parallelism. - Mary L. Bailey; Lawrence Snyder 001 (DAC, 1988)

Debugging Parallel Programs using Graphical Views. - Mary L. Bailey; David Socha; David Notkin (ICPP (2), 1988)

Voyeur: Graphical Views of Parallel Programs. - David Socha; Mary L. Bailey; David Notkin (Workshop on Parallel and Distributed Debugging, 1988)

Experiences with Poker. - David Notkin; Lawrence Snyder 001; David Socha; Mary L. Bailey; Bruce Forstall; Kevin Gates; Raymond Greenlaw; William G. Griswold; Thomas J. Holman; Richard Korry; Gemini Lasswell; Robert Mitchell; et al. (PPOPP/PPEALS, 1988)

A model for comparing synchronization strategies for parallel logic-level simulation. - Mary L. Bailey; Lawrence Snyder 001 (ICCAD, 1989)

Apex: two architectures for generating parametric curves and surfaces. - Tony DeRose; Mary L. Bailey; Bill Barnard; Robert Cypher; David Dobrikin; Carl Ebeling; Smaragda Konstantinidou; Larry McMurchie; Haim Mizrahi; Bill Yost (Vis. Comput., 1989)

Comparing Synchronization Protocols for Parallel Logic-Level Simulation. - Yi-Bing Lin; Edward D. Lazowska; Mary L. Bailey (ICPP (3), 1990)

Measuring the overhead in conservative parallel simulations of multicomputer programs. - Mary L. Bailey; Michael A. Pagels (WSC, 1991)

How circuit size affects parallelism. - Mary L. Bailey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A time-based model for investigating parallel logic-level simulation. - Mary L. Bailey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

How using busses in multicomputer programs affects conservative parallel simulation. - Mary L. Bailey; Michael A. Pagels; Kachung Kevin Wong (PADS, 1993)

A delay-based model for circuit parallelism. - Mary L. Bailey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

PathFinder: A Pattern-Based Packet Classifier. - Mary L. Bailey; Burra Gopal; Michael A. Pagels; Larry L. Peterson; Prasenjit Sarkar (OSDI, 1994)

Towards "on the fly" performance models for conservative asynchronous protocols. - Mary L. Bailey; Shane Walker (WSC, 1994)

Parallel Logic Simulation of VLSI Systems. - Mary L. Bailey; Jack V. Briner Jr.; Roger D. Chamberlain (ACM Comput. Surv., 1994)

Empirical Measurements of Overheads in Conservative Asynchronous Simulations. - Mary L. Bailey; Michael A. Pagels (ACM Trans. Model. Comput. Simul., 1994)

CNI: A High-Performance Network Interface for Workstation Clusters. - Prasenjit Sarkar; Mary L. Bailey (HPDC, 1996)

Using ZPL to Develop a Parallel Chaos Router Simulator. - Wilkey Richardson; Mary L. Bailey; William H. Sanders (WSC, 1996)

Adapting the Network Interface for High-Performance Computing: The CNI Approach. - Prasenjit Sarkar; Mary L. Bailey (J. Supercomput., 1997)