Semiparallel execution of compiled Lisp programs. - Masa-Aki Fukase; Tadao Nakamura (COMPSAC, 1991)

Parallel Processing and Hardware Support of Symbols. - Masa-Aki Fukase; Tadao Nakamura (ICTAI, 1993)

Scaling Up Of Wave Pipelines. - Masa-Aki Fukase; Ryusuke Egawa; Tomoaki Sato; Tadao Nakamura (VLSI Design, 2001)

Hardware/Software Co-design of a Secure Ubiquitous System. - Masa-Aki Fukase; Hiroki Takeda; Tomoaki Sato (CIS, 2006)

A Stream Cipher Engine for Ad-Hoc Security. - Masa-Aki Fukase; Tomoaki Sato (CIS, 2007)

Design and chip implementation of the ubiquitous processor HCgorilla. - Masa-Aki Fukase; Kazunori Noda; Atsuko Yokoyama; Tomoaki Sato (ASP-DAC, 2009)

A ubiquitous processor embedded with progressive cipher pipelines. - Masa-Aki Fukase; Atsuko Yokoyama; Tomoaki Sato (ACM Great Lakes Symposium on VLSI, 2009)

H/S Collaborative Development of a Ubiquitous Processor Free from Instruction Scheduling and Pipeline Disturbance. - Masa-Aki Fukase; Tomoaki Sato (ACIS-ICIS, 2010)

Design and chip implementation of an instruction scheduling free ubiquitous processor. - Masa-Aki Fukase; Ryosuke Murakami; Tomoaki Sato (ASP-DAC, 2010)

Development of a next generation ubiquitous processor chip. - Masa-Aki Fukase; Harunobu Uchiumi; Kazuki Narita; Tatsuya Takaki; Naomichi Mimura; Kohei Ichinohe; Tomoaki Sato; Atsushi Kurokawa (ISPACS, 2011)

Optimum design of the execution stage of embedded processors. - Masa-Aki Fukase; Atsushi Kurokawa; Kouhei Ichinohe; Tatsuya Takaki (ISCIT, 2012)

An interactive rewards card system embedded in smart phones and a cloud server. - Masa-Aki Fukase; Kohta Okamoto (GCCE, 2013)

Modeling of substrate contacts in TSV-based 3D ICs. - Masayuki Watanabe; Masa-Aki Fukase; Masashi Imai; Nanako Niioka; Tetsuya Kobayashi; Rosely Karel; Atsushi Kurokawa (3DIC, 2014)

Impact of on-chip interconnects on vertical signal propagation in 3D ICs. - Nanako Niioka; Masayuki Watanabe; Rosely Karel; Tetsuya Kobayashi; Masashi Imai; Masa-Aki Fukase; Atsushi Kurokawa (APCCAS, 2014)

Effect of substrate contacts on reducing crosstalk noise between TSVs. - Masayuki Watanabe; Rosely Karel; Nanako Niioka; Tetsuya Kobayashi; Masa-Aki Fukase; Masashi Imai; Atsushi Kurokawa (APCCAS, 2014)

Clock skew reduction for stacked chips using multiple source buffers. - Nanako Niioka; Masashi Imai; Masa-Aki Fukase; Yuuki Miura; Kaoru Furumi; Atsushi Kurokawa (ISCIT, 2015)

An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs. - Masayuki Watanabe; Nanako Niioka; Tetsuya Kobayashi; Rosely Karel; Masa-Aki Fukase; Masashi Imai; Atsushi Kurokawa (ISQED, 2015)

Signal Propagation Delay Model in Vertically Stacked Chips. - Nanako Niioka; Masayuki Watanabe; Masa-Aki Fukase; Masashi Imai; Atsushi Kurokawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)