A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture. - Masao Taguchi; Hiroyoshi Tomita; Toshiya Uchida; Yasuhiro Ohnishi; Kimiaki Sato; Taiji Ema; Masaaki Higashitani; Takashi Yabu (IEEE J. Solid State Circuits, 1991)

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput. - Ken Takeuchi; Yasushi Kameda; Susumu Fujimura; Hiroyuki Otake; Koji Hosono; Hitoshi Shiga; Yoshihisa Watanabe; Takuya Futatsuyama; Yoshihiko Shindo; Masatsugu Kojima; Makoto Iwai; Masanobu Shirakawa; et al. (ISSCC, 2006)

A 146-mm2 8-gb multi-level NAND flash memory with 70-nm CMOS technology. - Takahiko Hara; Koichi Fukuda; Kazuhisa Kanazawa; Noboru Shibata; Koji Hosono; Hiroshi Maejima; Michio Nakagawa; Takumi Abe; Masatsugu Kojima; Masaki Fujiu; Yoshiaki Takeuchi; Kazumi Amemiya; et al. (IEEE J. Solid State Circuits, 2006)

A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput. - Ken Takeuchi; Yasushi Kameda; Susumu Fujimura; Hiroyuki Otake; Koji Hosono; Hitoshi Shiga; Yoshihisa Watanabe; Takuya Futatsuyama; Yoshihiko Shindo; Masatsugu Kojima; Makoto Iwai; Masanobu Shirakawa; et al. (IEEE J. Solid State Circuits, 2007)

A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm. - Raul Cernea; Long Pham; Farookh Moogat; Siu Lung Chan; Binh Le; Yan Li; Shouchang Tsao; Taiyuan Tseng; Khanh Nguyen; Jason Li 001; Jayson Hu; Jong Park; et al. (ISSCC, 2008)

A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology. - Kazushige Kanda; Masaru Koyanagi; Toshio Yamamura; Koji Hosono; Masahiro Yoshihara; Toru Miwa; Yosuke Kato; Alex Mak; Siu Lung Chan; Frank Tsai; Raul Cernea; Binh Le; et al. (ISSCC, 2008)

A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate. - Yan Li; Seungpil Lee; Yupin Fong; Feng Pan; Tien-Chien Kuo; Jong Park; Tapan Samaddar; Hao Nguyen; Man Mui; Khin Htoo; Teruhiko Kamei; Masaaki Higashitani; et al. (ISSCC, 2008)

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS. - Cuong Trinh; Noboru Shibata; Takeshi Nakano; Mikio Ogawa; Jumpei Sato; Yoshikazu Takeyama; Katsuaki Isobe; Binh Le; Farookh Moogat; Nima Mokhlesi; Kenji Kozakai; Patrick Hong; et al. (ISSCC, 2009)

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology. - Raul Cernea; Long Pham; Farookh Moogat; Siu Lung Chan; Binh Le; Yan Li; Shouchang Tsao; Taiyuan Tseng; Khanh Nguyen; Jason Li 001; Jayson Hu; Jonghak Yuh; et al. (IEEE J. Solid State Circuits, 2009)

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate. - Yan Li; Seungpil Lee; Yupin Fong; Feng Pan; Tien-Chien Kuo; Jongmin Park; Tapan Samaddar; Hao Nguyen; Man Mui; Khin Htoo; Teruhiko Kamei; Masaaki Higashitani; et al. (IEEE J. Solid State Circuits, 2009)

A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology. - Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Toshiaki Edahiro; Takeshi Ogawa; et al. (ISSCC, 2011)

128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode. - Yan Li; Seungpil Lee; Ken Oowada; Hao Nguyen; Qui Nguyen; Nima Mokhlesi; Cynthia Hsu; Jason Li 001; Venky Ramachandra; Teruhiko Kamei; Masaaki Higashitani; Tuan Pham; et al. (ISSCC, 2012)

A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. - Noboru Shibata; Kazushige Kanda; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Kazuko Inuzuka; Naoaki Kanagawa; Yasuyuki Kajitani; et al. (ISSCC, 2012)

A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology. - Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Takeshi Ogawa; Toshiaki Edahiro; et al. (IEEE J. Solid State Circuits, 2012)

A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology. - Tz-Yi Liu; Tian Hong Yan; Roy Scheuerlein; Yingchang Chen; Jeffrey KoonYee Lee; Gopinath Balakrishnan; Gordon Yee; Henry Zhang; Alex Yap; Jingwen Ouyang; Takahiko Sasaki; Sravanti Addepalli; et al. (ISSCC, 2013)

A 130.7-mm2 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology. - Tz-Yi Liu; Tian Hong Yan; Roy Scheuerlein; Yingchang Chen; Jeffrey KoonYee Lee; Gopinath Balakrishnan; Gordon Yee; Henry Zhang; Alex Yap; Jingwen Ouyang; Takahiko Sasaki; Ali Al-Shamma; et al. (IEEE J. Solid State Circuits, 2014)

Low Cost 'On Pitch Select Gate' (OPS) Technology for 3D Flash Memory. - Abhijith Prakash; Xiang Yang; James Kai; Xiaochen Zhu; Henry Chin; Guirong Liang; Deepanshu Dutta; Masaaki Higashitani; Kazuki Isozumi; Shinsuke Yada; Sayako Nagamine; Kenichi Okabe; et al. (IMW, 2025)