A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode. - Kazuhiro Sawada; Takayasu Sakurai; Kazutaka Nogami; Katsuhiko Sato; Tsukasa Shirotori; Masakazu Kakuma; Shigeru Morita; Masaaki Kinugawa; Tetsuya Asami; Kazuhito Narita; Jun-Ichi Matsunaga; Akira Higuchi; et al. (IEEE J. Solid State Circuits, 1988)

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell. - Takayuki Ootani; Shigeyuki Hayakawa; Masakazu Kakumu; Akira Aona; Masaaki Kinugawa; Hideki Takeuchi; Kazuhiro Noguchi; Tomoaki Yabe; Katsuhiko Sato; Kenji Maeguchi; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1990)

A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. - Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Tetsu Nagamatsu; Shinichi Yoshioka; Kojiro Suzuki; Fumihiko Sano; Masayuki Norishima; Masayuki Murota; Makoto Kako; Masaaki Kinugawa; Masakazu Kakurnu; et al. (IEEE J. Solid State Circuits, 1996)