An acoustic measure for predicting recognition performance degradation. - Kazuya Takeda; Masaaki Kondo; Fumitada Itakura (ICASSP, 2000)

SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. - Masaaki Kondo; Hideki Okawara; Hiroshi Nakamura; Taisuke Boku (ICCD, 2000)

Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. - Hiroshi Nakamura; Masaaki Kondo; Taisuke Boku (Intelligent Memory Systems, 2000)

Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. - T. Ohneda; Masaaki Kondo; Masashi Imai; Hiroshi Nakamura (APCCAS (1), 2002)

Cache Line Impact on 3D PDE Solvers. - Masaaki Kondo; Mitsugu Iwamoto; Hiroshi Nakamura (ISHPC, 2002)

Software-controlled on-chip memory for high-performance and low-power computing. - Masaaki Kondo; Motonobu Fujita; Hiroshi Nakamura (SIGARCH Comput. Archit. News, 2002)

Data Movement Optimization for Software-Controlled On-Chip Memory. - Motonobu Fujita; Masaaki Kondo; Hiroshi Nakamura (Interaction between Compilers and Computer Architectures, 2004)

Dynamic Processor Throttling for Power Efficient Computations. - Masaaki Kondo; Hiroshi Nakamura (PACS, 2004)

Skewed Checkpointing for Tolerating Multi-Node Failures. - Hiroshi Nakamura; Takuro Hayashida; Masaaki Kondo; Yuya Tajima; Masashi Imai; Takashi Nanya (SRDS, 2004)

SCIMA-SMP: on-chip memory processor architecture for SMP. - Chikafumi Takahashi; Masaaki Kondo; Taisuke Boku; Daisuke Takahashi; Hiroshi Nakamura; Mitsuhisa Sato (WMPI, 2004)

A Small, Fast and Low-Power Register File by Bit-Partitioning. - Masaaki Kondo; Hiroshi Nakamura (HPCA, 2005)

Empirical Study for Optimization of Power-Performance with On-Chip Memory. - Chikafumi Takahashi; Mitsuhisa Sato; Daisuke Takahashi; Taisuke Boku; Hiroshi Nakamura; Masaaki Kondo; Motonobu Fujita (ISHPC, 2005)

Dynamic Instruction Cascading on GALS Microprocessors. - Hiroshi Sasaki 001; Masaaki Kondo; Hiroshi Nakamura (PATMOS, 2005)

Design Method of High Performance and Low Power Functional Units Considering Delay Variations. - Kouichi Watanabe; Masashi Imai; Masaaki Kondo; Hiroshi Nakamura; Takashi Nanya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

An intra-task dvfs technique based on statistical analysis of hardware events. - Hiroshi Sasaki 001; Yoshimichi Ikeda; Masaaki Kondo; Hiroshi Nakamura (Conf. Computing Frontiers, 2007)

Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. - Ryo Watanabe; Masaaki Kondo; Masashi Imai; Hiroshi Nakamura; Takashi Nanya (DATE, 2007)

Power reduction of chip multi-processors using shared resource control cooperating with DVFS. - Ryo Watanabe; Masaaki Kondo; Hiroshi Nakamura; Takashi Nanya (ICCD, 2007)

A High Performance Cluster System Design by Adaptie Power Control. - Masaaki Kondo; Yoshimichi Ikeda; Hiroshi Nakamura (IPDPS, 2007)

Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. - Masaaki Kondo; Hiroshi Sasaki 001; Hiroshi Nakamura (SIGARCH Comput. Archit. News, 2007)

A fine-grain dynamic sleep control scheme in MIPS R3000. - Naomi Seki; Lei Zhao; Jo Kei; Daisuke Ikebuchi; Yu Kojima; Yohei Hasegawa; Hideharu Amano; Toshihiro Kashima; Seidai Takeda; Toshiaki Shirai; Mitsutaka Nakata; Kimiyoshi Usami; et al. (ICCD, 2008)

Power-performance modeling of heterogeneous cluster-based web servers. - Hiroshi Sasaki 001; Takatsugu Oya; Masaaki Kondo; Hiroshi Nakamura (GRID, 2009)

Cooperative shared resource access control for low-power chip multiprocessors. - Noriko Takagi; Hiroshi Sasaki 001; Masaaki Kondo; Hiroshi Nakamura (ISLPED, 2009)

Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. - Kimiyoshi Usami; Toshiaki Shirai; Tatsunori Hashida; Hiroki Masuda; Seidai Takeda; Mitsutaka Nakata; Naomi Seki; Hideharu Amano; Mitaro Namiki; Masashi Imai; Masaaki Kondo; Hiroshi Nakamura (VLSI Design, 2009)

Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping. - Hiroshi Sasaki 001; Masaaki Kondo; Hiroshi Nakamura (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. - Daisuke Ikebuchi; Naomi Seki; Yu Kojima; M. Kamata; Lei Zhao; Hideharu Amano; Toshiaki Shirai; Satoshi Koyama; Tatsunori Hashida; Y. Umahashi; Hiroki Masuda; Kimiyoshi Usami; et al. (ASP-DAC, 2010)

Adaptive power gating for function units in a microprocessor. - Kimiyoshi Usami; Tatsunori Hashida; Satoshi Koyama; Tatsuya Yamamoto; Daisuke Ikebuchi; Hideharu Amano; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura (ISQED, 2010)

Geyser-2: The second prototype CPU with fine-grained run-time power gating. - Lei Zhao; Daisuke Ikebuchi; Yoshiki Saito; M. Kamata; Naomi Seki; Yu Kojima; Hideharu Amano; Satoshi Koyama; Tatsunori Hashida; Y. Umahashi; D. Masuda; Kimiyoshi Usami; et al. (ASP-DAC, 2011)

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. - Nobuaki Ozaki; Kimiyoshi Usami; Hideharu Amano; Mitaro Namiki; Hiroshi Nakamura; Masaaki Kondo (COOL Chips, 2011)

Cool Mega-Array: A highly energy efficient reconfigurable accelerator. - Nobuaki Ozaki; Yoshihiro Yasuda; Yoshiki Saito; Daisuke Ikebuchi; Masayuki Kimura; Hideharu Amano; Hiroshi Nakamura; Kimiyoshi Usami; Mitaro Namiki; Masaaki Kondo (FPT, 2011)

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. - Zhao Lei; Daisuke Ikebuchi; Kimiyoshi Usami; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura; Hideharu Amano (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. - Nobuaki Ozaki; Yoshihiro Yasuda; Mai Izawa; Yoshiki Saito; Daisuke Ikebuchi; Hideharu Amano; Hiroshi Nakamura; Kimiyoshi Usami; Mitaro Namiki; Masaaki Kondo (IEEE Micro, 2011)

FLAT: a GPU programming framework to provide embedded MPI. - Takefumi Miyoshi; Hidetsugu Irie; Keigo Shima; Hiroki Honda; Masaaki Kondo; Tsutomu Yoshinaga (GPGPU@ASPLOS, 2012)

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. - Yusuke Koizumi; Eiichi Sasaki; Hideharu Amano; Hiroki Matsutani; Yasuhiro Take; Tadahiro Kuroda; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPL, 2012)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. - Yusuke Koizumi; Hideharu Amano; Hiroki Matsutani; Noriyuki Miura; Tadahiro Kuroda; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPT, 2012)

Geyser. - Hiroshi Sasaki 001; Hideharu Amano; Kimiyoshi Usami; Masaaki Kondo; Mitaro Namiki; Hiroshi Nakamura (Handbook of Energy-Aware and Green Computing, 2012)

SMYLEref: A reference architecture for manycore-processor SoCs. - Masaaki Kondo; Son Truong Nguyen; Tomoya Hirao; Takeshi Soga; Hiroshi Sasaki 001; Koji Inoue (ASP-DAC, 2013)

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. - Yusuke Koizumi; Noriyuki Miura; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPL, 2013)

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. - Noriyuki Miura; Yusuke Koizumi; Eiichi Sasaki; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (Hot Chips Symposium, 2013)

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. - Hiroshi Nakamura; Weihan Wang; Yuya Ohta; Kimiyoshi Usami; Hideharu Amano; Masaaki Kondo; Mitaro Namiki (IEICE Trans. Electron., 2013)

A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards. - Son-Truong Nguyen; Masaaki Kondo; Tomoya Hirao; Koji Inoue (IEICE Trans. Inf. Syst., 2013)

A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. - Noriyuki Miura; Yusuke Koizumi; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (IEEE Micro, 2013)

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. - Kimiyoshi Usami; Masaru Kudo; Kensaku Matsunaga; Tsubasa Kosaka; Yoshihiro Tsurui; Weihan Wang; Hideharu Amano; Hiroaki Kobayashi; Ryuichi Sakamoto; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura (ASP-DAC, 2014)

Design and evaluation of fine-grained power-gating for embedded microprocessors. - Masaaki Kondo; Hiroaki Kobayashi; Ryuichi Sakamoto; Motoki Wada; Jun Tsukamoto; Mitaro Namiki; Weihan Wang; Hideharu Amano; Kensaku Matsunaga; Masaru Kudo; Kimiyoshi Usami; Toshiya Komoda; et al. (DATE, 2014)

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. - Kimiyoshi Usami; Makoto Miyauchi; Masaru Kudo; Kazumitsu Takagi; Hideharu Amano; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura (ISSoC, 2014)

A flexible hardware barrier mechanism for many-core processors. - Takeshi Soga; Hiroshi Sasaki 001; Tomoya Hirao; Masaaki Kondo; Koji Inoue (ASP-DAC, 2015)

Runtime multi-optimizations for energy efficient on-chip interconnections1. - Yuan He 002; Masaaki Kondo; Takashi Nakada; Hiroshi Sasaki 001; Shinobu Miwa; Hiroshi Nakamura (ICCD, 2015)

Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing. - Yuichi Inadomi; Tapasya Patki; Koji Inoue; Mutsumi Aoyagi; Barry Rountree; Martin Schulz 001; David K. Lowenthal; Yasutaka Wada; Keiichiro Fukazawa; Masatsugu Ueda; Masaaki Kondo; Ikuo Miyoshi (SC, 2015)

A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. - Atsushi Koshiba; Motoki Wada; Ryuichi Sakamoto; Mikiko Sato; Tsubasa Kosaka; Kimiyoshi Usami; Hideharu Amano; Masaaki Kondo; Hiroshi Nakamura; Mitaro Namiki (IEICE Trans. Electron., 2015)

Demand-Aware Power Management for Power-Constrained HPC Systems. - Cao Thang; Yuan He 002; Masaaki Kondo (CCGrid, 2016)

Opportunistic circuit-switching for energy efficient on-chip networks. - Yuan He 002; Masaaki Kondo (VLSI-SoC, 2016)

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. - Yuan He 002; Masaaki Kondo; Takashi Nakada; Hiroshi Sasaki 001; Shinobu Miwa; Hiroshi Nakamura (IEICE Trans. Inf. Syst., 2016)

An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. - Atsushi Koshiba; Mikiko Sato; Kimiyoshi Usami; Hideharu Amano; Ryuichi Sakamoto; Masaaki Kondo; Hiroshi Nakamura; Mitaro Namiki (IEICE Trans. Electron., 2016)

Cooling-Aware Job Scheduling and Node Allocation for Overprovisioned HPC Systems. - Thang Cao; Wei Huang; Yuan He 002; Masaaki Kondo (IPDPS, 2017)

Production Hardware Overprovisioning: Real-World Performance Optimization Using an Extensible Power-Aware Resource Management Framework. - Ryuichi Sakamoto; Thang Cao; Masaaki Kondo; Koji Inoue; Masatsugu Ueda; Tapasya Patki; Daniel A. Ellsworth; Barry Rountree; Martin Schulz 001 (IPDPS, 2017)

Building block multi-chip systems using inductive coupling through chip interface. - Hideharu Amano; Tadahiro Kuroda; Hiroshi Nakamura; Kimiyoshi Usami; Masaaki Kondo; Hiroki Matsutani; Mitaro Namiki (ISOCC, 2017)

Scalable deep neural network accelerator cores with cubic integration using through chip interface. - Ryuichi Sakamoto; Ryo Takata; Jun Ishii; Masaaki Kondo; Hiroshi Nakamura; Tetsui Ohkubo; Takuya Kojima; Hideharu Amano (ISOCC, 2017)

The Design and Implementation of Scalable Deep Neural Network Accelerator Cores. - Ryuichi Sakamoto; Ryo Takata; Jun Ishii; Masaaki Kondo; Hiroshi Nakamura; Tetsui Ohkubo; Takuya Kojima; Hideharu Amano (MCSoC, 2017)

Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning. - Shaswot Shresthamali; Masaaki Kondo; Hiroshi Nakamura (ACM Trans. Embed. Comput. Syst., 2017)

OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector. - Mineto Tsukada; Masaaki Kondo; Hiroki Matsutani (Euro-Par Workshops, 2018)

Analyzing Resource Trade-offs in Hardware Overprovisioned Supercomputers. - Ryuichi Sakamoto; Tapasya Patki; Thang Cao; Masaaki Kondo; Koji Inoue; Masatsugu Ueda; Daniel A. Ellsworth; Barry Rountree; Martin Schulz 001 (IPDPS, 2018)

A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems. - Yasutaka Wada; Yuan He 002; Thang Cao; Masaaki Kondo (SCFA, 2018)

A new device for fiducial registration of image-guided navigation system for liver RFA. - Nobutaka Doba; Hiroyuki Fukuda; Kazushi Numata; Yoshiteru Hao; Kouji Hara; Akito Nozaki; Masaaki Kondo; Makoto Chuma; Katsuaki Tanaka; Shigeo Takebayashi; Norihiro Koizumi; Akira Kobayashi; et al. (Int. J. Comput. Assist. Radiol. Surg., 2018)

An Adaptive Abnormal Behavior Detection using Online Sequential Learning. - Rei Ito; Mineto Tsukada; Masaaki Kondo; Hiroki Matsutani (CSE/EUC, 2019)

Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement Learning. - Shaswot Shresthamali; Masaaki Kondo; Hiroshi Nakamura (ICCD, 2019)

A Preliminary Evaluation of Building Block Computing Systems. - Sayaka Terashima; Takuya Kojima; Hayate Okuhara; Kazusa Musha; Hideharu Amano; Ryuichi Sakamoto; Masaaki Kondo; Mitaro Namiki (MCSoC, 2019)

Generation High resolution 3D model from natural language by Generative Adversarial Network. - Kentaro Fukamizu; Masaaki Kondo; Ryuichi Sakamoto (CoRR, 2019)

Energy-Efficient On-Chip Networks through Profiled Hybrid Switching. - Yuan He 002; Jinyu Jiao; Thang Cao; Masaaki Kondo (ACM Great Lakes Symposium on VLSI, 2020)

The Effectiveness of Low-Precision Floating Arithmetic on Numerical Codes: A Case Study on Power Consumption. - Ryuichi Sakamoto; Masaaki Kondo; Kohei Fujita; Tsuyoshi Ichimura; Kengo Nakajima (HPC Asia, 2020)

A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection. - Yang Qin; Hiroki Matsutani; Masaaki Kondo (iThings/GreenCom/CPSCom/SmartData/Cybermatics, 2020)

Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine. - Hiroki Oikawa; Tomoya Nishida; Ryuichi Sakamoto; Hiroki Matsutani; Masaaki Kondo (ITSC, 2020)

A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices. - Mineto Tsukada; Masaaki Kondo; Hiroki Matsutani (IEEE Trans. Computers, 2020)

Evaluation of SPEC CPU and SPEC OMP on the A64FX. - Yuetsu Kodama; Masaaki Kondo; Mitsuhisa Sato (CLUSTER, 2021)

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code. - Yosuke Ueno; Masaaki Kondo; Masamitsu Tanaka; Yasunari Suzuki; Yutaka Tabuchi (DAC, 2021)

Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL. - Yunjiao Ma; Yuan He 002; Yasutaka Wada; Wenchao Luo; Ryuichi Sakamoto; Masaaki Kondo (CANDAR (Workshops), 2021)

A Lightweight Interactive Graph Processing Library for Edge Computing in Smart Society. - Jun Zhou; Masaaki Kondo (CANDAR (Workshops), 2021)

Path Planning and Moving Obstacle Avoidance with Neuromorphic Computing. - Motoki Sakurai; Yosuke Ueno; Masaaki Kondo (ISR, 2021)

Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes. - Shaswot Shresthamali; Masaaki Kondo; Hiroshi Nakamura (MCSoC, 2021)

Local Traffic-Based Energy-Efficient Hybrid Switching for On-Chip Networks. - Yuan He 002; Jinyu Jiao; Masaaki Kondo (PDP, 2021)

Density-Based Data Selection and Management for Edge Computing. - Hiroki Oikawa; Masaaki Kondo (PerCom, 2021)

MLMG: Multi-Local and Multi-Global Model Aggregation for Federated Learning. - Yang Qin; Masaaki Kondo (PerCom Workshops, 2021)

Adaptive Resource Management for HPC Systems (Dagstuhl Seminar 21441). - Michael Gerndt; Masaaki Kondo; Barton P. Miller; Tapasya Patki (Dagstuhl Reports, 2021)

Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems. - Yuan He 002; Yasutaka Wada; Wenchao Luo; Ryuichi Sakamoto; Guanqin Pan; Thang Cao; Masaaki Kondo (IEICE Trans. Electron., 2021)

Body Bias Control on a CGRA based on Convex Optimization. - Takuya Kojima; Hayate Okuhara; Masaaki Kondo; Hideharu Amano (COOL CHIPS, 2022)

Hash Distributed A* on an FPGA. - Ryuichi Sakamoto; Yuriko Ezaki; Masaaki Kondo (HEART, 2022)

QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery. - Yosuke Ueno; Masaaki Kondo; Masamitsu Tanaka; Yasunari Suzuki; Yutaka Tabuchi (HPCA, 2022)

ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC. - Man Wu; Hiroki Matsutani; Masaaki Kondo (HPCC/DSS/SmartCity/DependSys, 2022)

Interactive and Reliable Graph Processing via the Edge-Cloud Collaboration Framework. - Jun Zhou; Masaaki Kondo (HPCC/DSS/SmartCity/DependSys, 2022)

FAWS: Fault-Aware Weight Scheduler for DNN Computations in Heterogeneous and Faulty Hardware. - Shaswot Shresthamali; Yuan He 002; Masaaki Kondo (ISPA/BDCloud/SocialCom/SustainCom, 2022)

Memory Bandwidth Conservation for SpMV Kernels Through Adaptive Lossy Data Compression. - Siyi Hu; Makiko Ito; Takahide Yoshikawa; Yuan He 002; Masaaki Kondo (PDCAT, 2022)

GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications. - Siyi Hu; Masaaki Kondo; Yuan He 002; Ryuichi Sakamoto; Hao Zhang; Jun Zhou; Hiroshi Nakamura (PDP, 2022)

On-Device Learning: A Neural Network Based Field-Trainable Edge AI. - Hiroki Matsutani; Mineto Tsukada; Masaaki Kondo (CoRR, 2022)

NEO-QEC: Neural Network Enhanced Online Superconducting Decoder for Surface Codes. - Yosuke Ueno; Masaaki Kondo; Masamitsu Tanaka; Yasunari Suzuki; Yutaka Tabuchi (CoRR, 2022)

Enabling circuit-switching in modern on-chip networks. - Jinyu Jiao; Yuan He 002; Thang Cao; Masaaki Kondo (Microprocess. Microsystems, 2022)

Exploiting Data Parallelism in Graph-Based Simultaneous Localization and Mapping: A Case Study with GPU Accelerations. - Junyuan Zheng; Yuan He 002; Masaaki Kondo (HPC Asia, 2023)

Enhancing Deep Reinforcement Learning with Compressed Sensing-based State Estimation. - Shaswot Shresthamali; Masaaki Kondo (MCSoC, 2023)

Accelerating Graph-Based SLAM through Data Parallelism and Mixed Precision on FPGAs. - Junfeng Wu; Yuan He 002; Masaaki Kondo (MCSoC, 2023)

Quantum Circuit Fidelity Improvement with Long Short-Term Memory Networks. - Yikai Mao; Shaswot Shresthamali; Masaaki Kondo (CoRR, 2023)

An edge re-ordering based acceleration architecture for improving data locality in graph analytics applications. - Siyi Hu; Masaaki Kondo; Yuan He 002; Ryuichi Sakamoto; Hao Zhang; Jun Zhou; Hiroshi Nakamura (Microprocess. Microsystems, 2023)

A Scalable Body Bias Optimization Method Toward Low-Power CGRAs. - Takuya Kojima; Hayate Okuhara; Masaaki Kondo; Hideharu Amano (IEEE Micro, 2023)

Addressing the Gap Between Training Data and Deployed Environment by On-Device Learning. - Kazuki Sunaga; Masaaki Kondo; Hiroki Matsutani (IEEE Micro, 2023)

An Edge-Cloud Collaboration Framework for Graph Processing in Smart Society. - Jun Zhou; Masaaki Kondo (IEEE Trans. Emerg. Top. Comput., 2023)

An Interactive and Reductive Graph Processing Library for Edge Computing in Smart Society. - Jun Zhou; Masaaki Kondo (IEICE Trans. Inf. Syst., 2023)

Evaluation of Performance and Power Consumption on Supercomputer Fugaku Using SPEC HPC Benchmarks. - Yuetsu Kodama; Masaaki Kondo; Mitsuhisa Sato (IEICE Trans. Electron., 2023)

Adaptive Lossy Data Compression Extended Architecture for Memory Bandwidth Conservation in SpMV. - Siyi Hu; Makiko Ito; Takahide Yoshikawa; Yuan He 002; Hiroshi Nakamura; Masaaki Kondo (IEICE Trans. Inf. Syst., 2023)

DAISM: Digital Approximate In-SRAM Multiplier-Based Accelerator for DNN Training and Inference. - Lorenzo Sonnino; Shaswot Shresthamali; Yuan He 002; Masaaki Kondo (DATE, 2024)

A High-Throughput Network Intrusion Detection System Using On-Device Learning on FPGA. - Man Wu; Masaaki Kondo (MCSoC, 2024)

Q-gen: A Parameterized Quantum Circuit Generator. - Yikai Mao; Shaswot Shresthamali; Masaaki Kondo (CoRR, 2024)

Quantum framework for Reinforcement Learning: integrating Markov Decision Process, quantum arithmetic, and trajectory search. - Thet Htar Su; Shaswot Shresthamali; Masaaki Kondo (CoRR, 2024)

Quantum-centric supercomputing for materials science: A perspective on challenges and future directions. - Yuri Alexeev; Maximilian Amsler; Marco Antonio Barroca; Sanzio Bassini; Torey Battelle; Daan Camps; David Casanova; Young Jay Choi; Frederic T. Chong; Charles Chung; Christopher Codella; Antonio D. Córcoles; et al. (Future Gener. Comput. Syst., 2024)

Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices. - Hiroki Matsutani; Masaaki Kondo; Kazuki Sunaga; Radu Marculescu (ASP-DAC, 2025)

Imperceptible Trojan Attacks to the Graph-Based Big Data Processing in Smart Society. - Jun Zhou; Masaaki Kondo (IEICE Trans. Inf. Syst., 2025)