Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications. - Shuhei Tanakamaru; Masafumi Doi; Ken Takeuchi (ISSCC, 2013)

NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture. - Shuhei Tanakamaru; Masafumi Doi; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage. - Tsukasa Tokutomi; Masafumi Doi; Shogo Hachiya; Atsuro Kobayashi; Shuhei Tanakamaru; Ken Takeuchi (ISSCC, 2015)

A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories. - Shuhei Tanakamaru; Masafumi Doi; Ken Takeuchi (IEICE Trans. Electron., 2015)