A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation. - Masafumi Onouchi; Tetsuya Yamada; Kimihiro Morikawa; Isamu Mochizuki; Hidetoshi Sekine (ASP-DAC, 2006)

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. - Hiroaki Shikano; Masaki Ito; Masafumi Onouchi; Takashi Todaka; Takanobu Tsunoda; Tomoyuki Kodama; Kunio Uchiyama; Toshihiko Odaka; Tatsuya Kamei; Ei Nagahama; Manabu Kusaoke; Yusuke Nitta; et al. (IEEE J. Solid State Circuits, 2008)

Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. - Masafumi Onouchi; Keisuke Toyama 003; Tohru Nojiri; Makoto Sato; Masayoshi Mase; Jun Shirako; Mikiko Sato; Masashi Takada; Masayuki Ito; Hiroyuki Mizuno; Mitaro Namiki; Keiji Kimura; et al. (ICPP, 2009)

A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. - Masafumi Onouchi; Yusuke Kanno; Makoto Saen; Shigenobu Komatsu; Yoshihiko Yasu; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2010)

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process. - Masafumi Onouchi; Kazuo Otsuga; Yasuto Igarashi; Toyohito Ikeya; Sadayuki Morita; Koichiro Ishibashi; Kazumasa Yanagisawa (A-SSCC, 2011)

An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. - Kazuo Otsuga; Masafumi Onouchi; Yasuto Igarashi; Toyohito Ikeya; Sadayuki Morita; Koichiro Ishibashi; Kazumasa Yanagisawa (SoCC, 2012)