A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. - Go Matsukawa; Yohei Nakata; Yuta Kimi; Yasuo Sugure; Masafumi Shimozawa; Shigeru Oho; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ARCS Workshops, 2014)

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. - Go Matsukawa; Yohei Nakata; Yasuo Sugure; Shigeru Oho; Yuta Kimi; Masafumi Shimozawa; Shuhei Yoshida; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2015)