A Parallel Searching Scheme for Multiprocessor Systems and Its Application to Combinatorial Problems. - Masaharu Imai; Yuuji Yoshida; Teruo Fukumura (IJCAI, 1979)

The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System. - Masaharu Imai; Yuuji Tateizumi; Yuuji Yoshida; Teruo Fukumura (ICDCS, 1984)

Implementation of Parallel Prolog on Tree Machines. - Hajime Miura; Masaharu Imai; Masafumi Yamashita; Toshihide Ibaraki (FJCC, 1986)

Parallel searches of game trees. - Hiromoto Usui; Masafumi Yamashita; Masaharu Imai; Toshihide Ibaraki (Syst. Comput. Jpn., 1987)

Reconfiguration of a fault-tolerant rectangular systolic array. - Yoshinao Suzuki; Tomio Hirata; Masaharu Imai; Masafumi Yamashita; Toshihide Ibaraki (Syst. Comput. Jpn., 1988)

Computational complexity of the file allocation problem in distributed database systems. - Hiroshi Yamasaki; Tomio Hirata; Masaharu Imai; Toshihide Ibaraki (Syst. Comput. Jpn., 1988)

An Integrated Design Environment for Application Specific Integrated Processor. - Jun Sato; Masaharu Imai; Tetsuya Hakata; Alauddin Y. Alomary; Nobuyuki Hikichi (ICCD, 1991)

An integer programming approach to instruction implementation method selection problem. - Masaharu Imai; Jun Sato; Alauddin Alomary; Nobuyuki Hikichi (EURO-DAC, 1992)

PEAS-I: A hardware/software co-design system for ASIPs. - Alauddin Alomary; Takeharu Nakata; Yoshimichi Honma; Jun Sato; Nobuyuki Hikichi; Masaharu Imai (EURO-DAC, 1993)

An ASIP instruction set optimization algorithm with functional module sharing constraint. - Alauddin Alomary; Takeharu Nakata; Yoshimichi Honma; Masaharu Imai; Nobuyuki Hikichi (ICCAD, 1993)

A hardware/software codesign method for pipelined instruction set processor using adaptive database. - Nguyen-Ngoc Bình; Masaharu Imai; Akichika Shiomi; Nobuyuki Hikichi (ASP-DAC, 1995)

Future direction of synthesizability and interoperability of HDL's: part 1. - Masaharu Imai; Eugenio Villar (ASP-DAC, 1995)

Future direction of synthesizabilty and interoperability of HDL's: part 2. - Eugenio Villar; Masaharu Imai (ASP-DAC, 1995)

A hardware/software partitioning algorithm for pipelined instruction set processor. - Nguyen-Ngoc Bình; Masaharu Imai; Nobuyuki Hikichi (EURO-DAC, 1995)

A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. - Nguyen-Ngoc Bình; Masaharu Imai; Akichika Shiomi; Nobuyuki Hikichi (DAC, 1996)

A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs. - Masaharu Imai; Nguyen-Ngoc Bình; Akichika Shiomi (EURO-DAC, 1996)

ASPDAC 1995: HDL synthesizability and interoperability. - Masaharu Imai; Eugenio Villar (IEEE Des. Test Comput., 1996)

VLSI implementation and evaluation of a real-time operating system. - Takumi Nakano; Andy Utama; Akichika Shiomi; Masaharu Imai; Mitsuyoshi Itabashi (Syst. Comput. Jpn., 1996)

VLSI implementation of a real-time operating system. - Takumi Nakano; Yoshiki Komatsudaira; Akichika Shiomi; Masaharu Imai (ASP-DAC, 1997)

A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. - Nguyen-Ngoc Bình; Masaharu Imai; Yoshinori Takeuchi (ASP-DAC, 1998)

Application of FHM-Based Design Method to Scalable 2-D DCT Processor. - Eiichirou Shigehara; Yoshinori Takeuchi; Masaharu Imai; Tsutomu Kimura (EUROMICRO, 1999)

A programmable processor with multiple functional units and banked registers for general purpose numerical processing. - Takafumi Morifuji; Yoshinori Takeuchi; Masaharu Imai (ICASSP, 1999)

One language or more?: how can we design an SoC at a system level? - Masaharu Imai; Gary Smith 001; Steven Schulz; Karen Bartleson; Daniel Gajski; Wolfgang Rosenstiel; Peter Flake; Hiroto Yasuura (ASP-DAC, 2000)

PEAS-III: An ASIP Design Environment. - Makiko Itoh; Shigeaki Higaki; Yoshinori Takeuchi; Akira Kitajima; Masaharu Imai; Jun Sato; Akichika Shiomi (ICCD, 2000)

Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. - Akira Kitajima; Makiko Itoh; Jun Sato; Akichika Shiomi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2001)

VLSI Implementation of Fractal Image Compression Processor for Moving Pictures. - Hideki Yamauchi; Yoshinori Takeuchi; Masaharu Imai (EUROMICRO, 2001)

Design space exploration for DSP applications using the ASIP development system PEAS-III. - Shinsuke Kobayashi; Kentaro Mita; Yoshinori Takeuchi; Masaharu Imai (ICASSP, 2002)

Design of Application Specific CISC Using PEAS-III. - Akira Kitajima; Toshiyuki Sasaki; Yoshinori Takeuchi; Masaharu Imai (IEEE International Workshop on Rapid System Prototyping, 2002)

A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors. - Shinsuke Kobayashi; Kentaro Mita; Yoshinori Takeuchi; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III. - Shinsuke Kobayashi; Kentaro Mita; Yoshinori Takeuchi; Masaharu Imai (ICASSP (2), 2003)

A Code Selection Method for SIMD Processors with PACK Instructions. - Hiroaki Tanaka; Shinsuke Kobayashi; Yoshinori Takeuchi; Keishi Sakanushi; Masaharu Imai (SCOPES, 2003)

Foreword. - Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Synthesizable HDL generation method for configurable VLIW processors. - Yuki Kobayashi; Shinsuke Kobayashi; Koji Okuda; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2004)

Architecture-Level Performance Estimation for IP-Based Embedded Systems. - Kyoko Ueda; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (DATE, 2004)

Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. - H. M. AbdElSalam; Shinsuke Kobayashi; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ICDCS Workshops, 2004)

S-sequence: a new floorplan representation method preserving room abutment relationships. - Yohei Ishimaru; Keishi Sakanushi; Shinsuke Kobayashi; Yoshinori Takeuchi; Masaharu Imai (ISCAS (4), 2004)

Enabling RTOS simulation modeling in a system level design language. - M. Abdelsalam Hassan; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2005)

Verification Challenges in Configurable Processor Design with ASIP Meister. - Masaharu Imai; Akira Kitajima (CHARME, 2005)

RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. - M. Abdelsalam Hassan; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (DATE, 2005)

Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. - Yuki Kobayashi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Masaharu Imai (ESTIMedia, 2005)

Pack instruction generation for media pUsing multi-valued decision diagram. - Hiroaki Tanaka; Yoshinori Takeuchi; Keishi Sakanushi; Masaharu Imai; Yutaka Ota; Nobu Matsumoto; Masaki Nakagawa (CODES+ISSS, 2006)

Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model. - Ittetsu Taniguchi; Keishi Sakanushi; Kyoko Ueda; Yoshinori Takeuchi; Masaharu Imai (VLSI-SoC (Selected Papers), 2006)

Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. - Ittetsu Taniguchi; Kyoko Ueda; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (VLSI-SoC, 2006)

A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. - Takeshi Shiro; Masaaki Abe; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2007)

A low power VLIW processor generation method by means of extracting non-redundant activation conditions. - Hirofumi Iwato; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (CODES+ISSS, 2007)

A Block-Floating-Point Processor for Rapid Application Development. - Hiroaki Tanaka; Yoshinori Takeuchi; Keishi Sakanushi; Masaharu Imai; Shiro Kobayashi (ICASSP (2), 2007)

Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram. - Hiroaki Tanaka; Yoshinori Takeuchi; Keishi Sakanushi; Masaharu Imai; Hiroki Tagawa; Yutaka Ota; Nobu Matsumoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. - Yuki Kobayashi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Masaharu Imai (ACM Trans. Design Autom. Electr. Syst., 2007)

Operation shuffling over cycle boundaries for low energy L0 clustering. - Yuki Kobayashi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Masaharu Imai (ASAP, 2008)

Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling. - Yuki Kobayashi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. - Ittetsu Taniguchi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2009)

Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor. - Takuji Hieda; Hiroaki Tanaka; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors. - Ittetsu Taniguchi; Praveen Raghavan; Murali Jayapala; Francky Catthoor; Yoshinori Takeuchi; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems. - Hassan A. Youness; Keishi Sakanushi; Yoshinori Takeuchi; Ashraf Salem; Abdel-Moniem Wahdan; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A new compilation technique for SIMD code generation across basic block boundaries. - Hiroaki Tanaka; Yutaka Ota; Nobu Matsumoto; Takuji Hieda; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2010)

Two-stage configurable decoder model for multiple forward error correction standards. - Ittetsu Taniguchi; Ayataka Kobayashi; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ESTIMedia, 2010)

Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm. - Hassan A. Youness; Abdel-Moniem Wahdan; Mohammed Hassan; Ashraf Salem; Mohammed Moness; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ISCAS, 2010)

Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). - Masaharu Imai; Yoshinori Takeuchi; Keishi Sakanushi; Nagisa Ishiura (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. - Hirofumi Iwato; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors. - Takahiro Kumura; Soichiro Taga; Nagisa Ishiura; Yoshinori Takeuchi; Masaharu Imai (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Electronic Triage System: Casualties Monitoring System in the Disaster Scene. - Keishi Sakanushi; Takuji Hieda; Taichiro Shiraishi; Yasumasa Ode; Yoshinori Takeuchi; Masaharu Imai; Teruo Higashino; Hiroshi Tanaka (3PGCIC, 2011)

Biological information sensing technologies for medical, health care, and wellness applications. - Masaharu Imai; Yoshinori Takeuchi; Keishi Sakanushi; Hirofumi Iwato (ASP-DAC, 2011)

Automated architecture exploration for low energy reconfigurable AGU. - Ittetsu Taniguchi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ISOCC, 2011)

Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design. - Ittetsu Taniguchi; Ayataka Kobayashi; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion. - Sho Ninomiya; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (MCSoC, 2012)

On-chip Communication Buffer Architecture Optimization Considering Bus Width. - Salita Sombatsiri; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (MCSoC, 2012)

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring. - Hirofumi Iwato; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (IEICE Trans. Electron., 2012)

Error analysis of an estimation method using RTT for available bandwidth of a bottleneck link. - Masaharu Imai; Takayuki Ozawa; Yoshio Sugizaki; Koichi Asatani (APNOMS, 2013)

An efficient lossless data compression method based on exponential-Golomb coding for biomedical information and its implementation using ASIP technology. - Shoko Nakatsuka; Takashi Hamabe; Yoshinori Takeuchi; Masaharu Imai (BioCAS, 2013)

A new estimation method using RTT for available bandwidth of a bottleneck link. - Masaharu Imai; Yoshio Sugizaki; Koichi Asatani (ICOIN, 2013)

Electronic triage system for continuously monitoring casualties at disaster scenes. - Keishi Sakanushi; Takuji Hieda; Taichiro Shiraishi; Yasumasa Ode; Yoshinori Takeuchi; Masaharu Imai; Teruo Higashino; Hiroshi Tanaka (J. Ambient Intell. Humaniz. Comput., 2013)

An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology. - Tomoki Sugiura; Shoko Nakatsuka; Jaehoon Yu; Yoshinori Takeuchi; Masaharu Imai (BioCAS, 2014)

A New Available Bandwidth Estimation Method Using RTT for a Bottleneck Link. - Masaharu Imai; Yoshio Sugizaki; Koichi Asatani (IEICE Trans. Commun., 2014)

A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems. - Tomoki Sugiura; Jaehoon Yu; Yoshinori Takeuchi; Masaharu Imai (BioCAS, 2015)

Cortical neural excitations in rats in vivo with using a prototype of a wireless multi-channel microstimulation system. - Yuki Hayashida; Yuichi Umehira; Kouki Takatani; Shigetoshi Futami; Seiji Kameda; Takatsugu Kamata; Arif Ullah Khan; Yoshinori Takeuchi; Masaharu Imai; Tetsuya Yagi (EMBC, 2015)

Preliminary study of a new home healthcare monitoring to prevent the recurrence of stroke. - Toshiyo Tamura; Masaki Sekine; Zunyi Tang; Masaki Yoshida; Yoshinori Takeuchi; Masaharu Imai (EMBC, 2015)

An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC. - Salita Sombatsiri; Yoshinori Takeuchi; Masaharu Imai (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis. - Tomoki Sugiura; Arif Ullah Khan; Jaehoon Yu; Yoshinori Takeuchi; Seiji Kameda; Takatsugu Kamata; Yuki Hayashida; Tetsuya Yagi; Masaharu Imai (BioCAS, 2016)

Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface. - Masaharu Imai; Yoshinori Takeuchi; Jun Ohta; Gregg Jørgen Suaning; Chung-Yu Wu; Napoleon Torres-Martinez (ASP-DAC, 2017)

Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty. - Fumika Tanabe; Shusuke Yoshimoto; Yuki Noda; Teppei Araki; Takafumi Uemura; Yoshinori Takeuchi; Masaharu Imai; Tsuyoshi Sekitani (EMBC, 2017)

Deformable Part Model Based Arrhythmia Detection Using Time Domain Features. - Yuuka Hirao; Yoshinori Takeuchi; Masaharu Imai; Jaehoon Yu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems. - Tomoki Sugiura; Masaharu Imai; Jaehoon Yu; Yoshinori Takeuchi (J. Inf. Process., 2017)

Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation. - Koichi Mitsunari; Yoshinori Takeuchi; Masaharu Imai; Jaehoon Yu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

EMoDi: Entity-Enhanced Momentum-Difference Contrastive Learning for Semantic-Aware Verification of Scientific Information. - Ze Yang; Yimeng Sun; Takao Nakaguchi; Masaharu Imai (ICKG, 2023)