A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. - Eiji Fujiwara; Masaharu Tanaka (DFT, 1993)

Defect-Tolerant WSI File Memory System Using Address Permutation for Spare Allocation. - Eiji Fujiwara; Masaharu Tanaka (IEICE Trans. Inf. Syst., 1995)

On-Line Compression of High Precision Printer Images by Evolvable Hardware. - Mehrdad Salami; Hidenori Sakanashi; Masaharu Tanaka; Masaya Iwata; Takio Kurita; Tetsuya Higuchi (Data Compression Conference, 1998)

Data Compression for Digital Color Electrophotographic Printer with Evolvable Hardware. - Masaharu Tanaka; Hidenori Sakanashi; Mehrdad Salami; Masaya Iwata; Takio Kurita; Tetsuya Higuchi (ICES, 1998)

Multiroute planning for aircraft using genetic algorithms. - Masaharu Tanaka; Masanobu Mizoguchi; Toshiaki Tange; Isao Takami; Shinji Suzuki (Syst. Comput. Jpn., 2004)

A Redundant Design Approach with Diversity of FPGA Resource Mapping. - Yudai Shirakura; Taisei Segawa; Yuichiro Shibata; Kenichi Morimoto; Masaharu Tanaka; Masanori Nobe; Hidenori Maruta; Fujio Kurokawa (ARC, 2016)

An FPGA Based Heterogeneous Redundant Control System Using Controller Virtualization. - Masaharu Tanaka; Haruhi Eto; Nobumasa Matsui; Fujio Kurokawa (CISIS, 2017)

A Study of FPGA Instance Based PLC Architecture Design and Automatic Generation Algorithm of Logic Code. - Renya Yamamoto; Masaharu Tanaka; Haruhi Eto; Fujio Kurokawa (CISIS, 2018)