Information and communication technology infrastructure and management for collaboration with regional universities and colleges. - Takashi Yamanoue; Robert J. Fouser; Tomohito Wada; Masayasu Hidaka; Yusei Suzuki; Masaharu Terada; Akira Takenoshita; Yutoku Beppu; Yoko Nedachi; Koji Yukawa; Holmes Rodriguez; Katsuyuki Suenaga; et al. (SIGUCCS, 2011)

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. - Shusuke Yoshimoto; Masaharu Terada; Youhei Umeki; Shunsuke Okumura; Atsushi Kawasumi; Toshikazu Suzuki; Shinichi Moriwaki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2012)

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. - Masaharu Terada; Shusuke Yoshimoto; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2012)

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Electron. Express, 2012)

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2012)

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ASP-DAC, 2013)