Proposal for fully automated mail processing system for the 21st century. - Masaharu Wada (Pattern Recognit. Lett., 1993)

A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM. - Shinji Miyano; Kenji Numata; Katsuhiko Sato; Tomoaki Yabe; Masaharu Wada; Ryo Haga; Motohiro Enkaku; Masazumi Shiochi; Yutaka Kawashima; Masayuki Iwase; Masahisa Ohgata; Junpei Kumagai; et al. (IEEE J. Solid State Circuits, 1995)

A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator. - Tomoaki Yabe; Shinji Miyano; Katsuhiko Sato; Masaharu Wada; Ryo Haga; Osamu Wada; Motohiro Enkaku; Takehiko Hojyo; Kenichiro Mimoto; Masaaki Tazawa; Tsutomu Ohkubo; Kenji Numata (IEEE J. Solid State Circuits, 1998)

A 65nm low-power embedded DRAM with extended data-retention sleep mode. - Takeshi Nagai; Masaharu Wada; Hitoshi Iwai; Mariko Kaku; Atsushi Suzuki; Tomohisa Takai; Naoko Itoga; Takayuki Miyazaki; Hiroyuki Takenaka; Takehiko Hojo; Shinji Miyano (ISSCC, 2006)

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. - Mariko Kaku; Hitoshi Iwai; Takeshi Nagai; Masaharu Wada; Atsushi Suzuki; Tomohisa Takai; Naoko Itoga; Takayuki Miyazaki; Takayuki Iwai; Hiroyuki Takenaka; Takehiko Hojo; Shinji Miyano; et al. (ISSCC, 2008)