A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. - Toshinori Hosokawa; Hiroshi Date; Masahide Miyazaki; Michiaki Muraoka; Hideo Fujiwara (Asian Test Symposium, 2003)

A DFT Selection Method for Reducing Test Application Time of System-on-Chips. - Masahide Miyazaki; Toshinori Hosokawa; Hiroshi Date; Michiaki Muraoka; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2004)

A memory grouping method for sharing memory BIST logic. - Masahide Miyazaki; Tomokazu Yoneda; Hideo Fujiwara (ASP-DAC, 2006)

A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. - Masahide Miyazaki; Tomokazu Yoneda; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2006)