Voltage limiters for DRAMs with substrate-plate-electrode memory cells. - Toshio Takeshima; Masahide Takada; Toshiyuki Shimizu; Takuya Katoh; Mitsuru Sakamoto (IEEE J. Solid State Circuits, 1988)

A BIST scheme using microprogram ROM for large capacity memories. - Hiroki Koike; Toshio Takeshima; Masahide Takada (ITC, 1990)

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM. - Toshio Takeshima; Masahide Takada; Hiroki Koike; Hiroshi Watanabe; Shigeru Koshimaru; Kenjiro Mitake; Wataru Kikuchi; Takaho Tanigawa; Tatsunori Murotani; Kenji Noda; Kazuhiro Tasaka; Koji Yamanaka; et al. (IEEE J. Solid State Circuits, 1990)

A 5-ns 1-Mb ECL BiCMOS SRAM. - Masahide Takada; Kazuyuki Nakamura; Toshio Takeshima; Koichiro Furuta; Tohru Yamazaki; Kiyotaka Imai; Susumu Ohi; Yumi Sekine; Yukio Minato; Hisamitsu Kimuto (IEEE J. Solid State Circuits, 1990)

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM. - Kazuyuki Nakamura; Takashi Oguri; Takao Atsumo; Masahide Takada; Atsushi Ikemoto; Hisamitsu Suzuki; Tadashi Nishigori; Tohru Yamazaki (IEEE J. Solid State Circuits, 1992)

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. - Akira Tanabe; Toshio Takeshima; Hiroki Koike; Yoshiharu Aimoto; Masahide Takada; Toshiyuki Ishijima; Naoki Kasai; Hiromitsu Hada; Kentaro Shibahara; Takemitsu Kunio; Takaho Tanigawa; Takanori Saeki; et al. (IEEE J. Solid State Circuits, 1992)

Memory LSI reliability. - Masao Fukuma; Hiroshi Furuta; Masahide Takada (Proc. IEEE, 1993)

A 300-MHz 16-b BiCMOS video signal processor. - Toshiaki Inoue; Junichi Goto; Masakazu Yamashina; Kazumasa Suzuki; Masahiro Nomura; Youichi Koseki; Tohru Kimura; Takao Atsumo; Masato Motomura; Benjamin S. Shih; Tadahiko Horiuchi; Nobuhisa Hamatake; et al. (IEEE J. Solid State Circuits, 1993)

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. - Kazuyuki Nakamura; Shigeru Kuhara; Tohru Kimura; Masahide Takada; Hisamitsu Suzuki; Hiroshi Yoshida; Tohru Yamazaki (IEEE J. Solid State Circuits, 1994)

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. - Hitoshi Okamura; Hideo Toyoshima; Koichi Takeda; Takashi Oguri; Satoshi Nakamura; Masahide Takada; Kiyotaka Imai; Yasushi Kinoshita; Hiroshi Yoshida; Tom Yamazaki (IEEE J. Solid State Circuits, 1995)

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme. - Hiraki Koike; Tetsuya Otsuki; Tohru Kimura; Masao Fukuma; Yoshihiro Hayashi; Yukihiko Maejima; Kazushi Amanuma; Nobuhira Tanabe; Takeo Matsuki; Shinobu Saito; Tsuneo Takeuchi; Souta Kobayashi; et al. (IEEE J. Solid State Circuits, 1996)

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump. - Hitoshi Okamura; Takao Atsumo; Koichi Takeda; Masahide Takada; Kiyotaka Imai; Yasushi Kinoshita; Tom Yamazaki (IEEE J. Solid State Circuits, 1996)

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. - Hideo Toyoshima; Shigeru Kuhara; Koichi Takeda 001; Kazuyuki Nakamura; Hiloshi Okamura; Masahide Takada; Hisamitsu Suzuki; Hiroshi Yoshida; Tohru Yamazaki (IEEE J. Solid State Circuits, 1996)