Extracting distance from defocused images with different aperture sizes. - Masahiko Iwane (Syst. Comput. Jpn., 1992)

Tagged communication and synchronization memory for multiprocessor-on-a-chip. - Masahiko Iwane; Akira Yamawaki 002; Makoto Tanaka (Syst. Comput. Jpn., 2001)

Organization of Shared Memory with Synchronization for Multiprocessor-on-a-chip. - Akira Yamawaki 002; Masahiko Iwane (ICPADS, 2002)

Evaluation of mechanisms introduced to improve performance of TSVM cache. - Akira Yamawaki 002; Masahiko Iwane (Parallel and Distributed Computing and Networks, 2004)

An efficient parallel processing using a cache memory with synchronization on a Soc-multiprocessor. - Akira Yamawaki 002; Masahiko Iwane (Circuits, Signals, and Systems, 2005)

Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. - Akira Yamawaki 002; Masahiko Iwane (ISPAN, 2005)

A Programmable Load/Store Unit on C-based Hardware Design for FPGA. - Akira Yamawaki 002; Masahiko Iwane (FPT, 2007)

An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip. - Akira Yamawaki 002; Masahiko Iwane (ICPADS, 2007)

An FPGA implementation of a DWT with 5/3 filter using semi-programmable hardware. - Akira Yamawaki 002; Kazuharu Morita; Masahiko Iwane (APCCAS, 2008)

An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware. - Akira Yamawaki 002; Seiichi Serikawa; Masahiko Iwane (ERSA, 2009)

An intermediate hardware model with load/store unit for C to FPGA. - Akira Yamawaki 002; Masahiko Iwane (FPGA, 2009)

An Efficient Hardware Architecture from C Program with Memory Access to Hardware. - Akira Yamawaki 002; Seiichi Serikawa; Masahiko Iwane (ICCSA (2), 2010)