Two-Dimensional Layout Synthesis for Large-Scale CMOS Circuits. - Katsunori Tani; Kyoichi Izumi; Masahiko Kashimura; Tsuneo Matsuda; Takashi Fujii (ICCAD, 1991)

Fault-tolerant architecture in a cache memory control LSI. - Yasushi Ooi; Masahiko Kashimura; Hidenori Takeuchi; Eiji Kawamura (IEEE J. Solid State Circuits, 1992)