A 24-b 50-ns digital image signal processor. - Shin-ichi Nakagawa; Hideyuki Terane; Tetsuya Matsumura; Hiroshi Segawa; Masahiko Yoshimoto; Hirofumi Shinohara; Shuichi Kato; Masahiro Hatanaka; Hideo Ohira; Yoshiaki Kato; Mamoru Iwatsuki; Kinya Tabuchi; et al. (IEEE J. Solid State Circuits, 1990)

A 100-MHz 2-D discrete cosine transform core processor. - Shin-ichi Uramoto; Yoshitsugu Inoue; Akihiko Takabatake; Jun Takeda; Yukihiro Yamashita; Hideyuki Terane; Masahiko Yoshimoto (IEEE J. Solid State Circuits, 1992)

A highly-parallel DSP architecture for image recognition. - Hiroyuki Kawai; Yoshitugu Inoue; Robert Streitenberger; Masahiko Yoshimoto (ICASSP, 1995)

A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search. - Kazuya Ishihara; Shinichi Masuda; Shin-ichi Hattori; Hirofumi Nishikawa; Yoshihide Ajioka; Tsuyoshi Yamada; Hiroyuki Amishiro; Shin-ichi Uramoto; Masahiko Yoshimoto; Tadashi Sumi (IEEE J. Solid State Circuits, 1995)

Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video. - T. Kamemaru; Hideo Ohira; H. Suzuki; Ken'ichi Asano; Masahiko Yoshimoto; Tokumichi Murakami (CICC, 2000)

MPEG-2 4: 2: 2@HL encoder chip set. - Hidenori Sato; Hideo Ohira; Masahiko Kazayama; Ayako Harada; Masahiko Yoshimoto; Okikazu Tanno; Satoshi Kumaki; Kazuya Ishibara; Atsuo Hanami; Tetsuya Mutsumura (ISCAS, 2000)

An image sensor with fast extraction of objects' positions - rough vision processor. - Akira Watanabe; Osamu Tooyama; Masayuki Miyama; Masahiko Yoshimoto; Junichi Akita (ICIP (2), 2001)

An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. - Masayuki Miyama; Osamu Tooyama; N. Takamatsu; T. Kodake; K. Nakamura; A. Kato; Junichi Miyakoshi; K. Hashimoto; Shigenobu Komatsu; M. Yagi; Masao Morimoto; Kazuo Taki; et al. (CICC, 2002)

A sub-mW MPEG-4 motion estimation processor core for mobile video application. - Junichi Miyakoshi; Yuri Kuroda; Masayuki Miyama; Kosuke Imamura; Hideo Hashimoto; Masahiko Yoshimoto (CICC, 2003)

The development and impact on business of the world's first live video streaming distribution platform for 3G mobile videophone terminals. - Hideo Ohira; Mitsuru Kodama; Masahiko Yoshimoto (Int. J. Electron. Bus., 2003)

A world first development of a multipoint videophone system over 3G-324M protocol. - Hideo Ohira; Mitsuru Kodama; Masahiko Yoshimoto (Int. J. Mob. Commun., 2003)

A sub-mW MPEG-4 motion estimation processor core for mobile video application. - Masayuki Miyama; Junichi Miyakoshi; Yuki Kuroda; Kousuke Imamura; Hideo Hashimoto; Masahiko Yoshimoto (IEEE J. Solid State Circuits, 2004)

Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era. - Kentaro Kawakami; Miwako Kanamori; Yasuhiro Morita; Jun Takemura; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. - Junichi Miyakoshi; Yuichiro Murachi; Koji Hamano; Tetsuro Matsuno; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Electron., 2005)

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. - Yuichiro Murachi; Koji Hamano; Tetsuro Matsuno; Junichi Miyakoshi; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Impact of Aggregation Efficiency on GIT Routing forWireless Sensor Networks. - Takafumi Aonishi; Takashi Matsuda; Shinji Mikami; Hiroshi Kawaguchi 001; Chikara Ohta; Masahiko Yoshimoto (ICPP Workshops, 2006)

A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. - Hidehiro Fujiwara; Koji Nii; Junichi Miyakoshi; Yuichiro Murachi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2006)

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. - Junichi Miyakoshi; Yuichiro Murachi; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto; Tetsuro Matsuno (VLSI-SoC, 2006)

A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90NM Risc Processor. - Kentaro Kawakami; Miwako Kanamori; Yasuhiro Morita; Jun Takemura; Hideo Ohira; Masayuki Miyama; Masahiko Yoshimoto (Intell. Autom. Soft Comput., 2006)

A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline. - Kentaro Kawakami; Jun Takemura; Mitsuhiko Kuroda; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks. - Shinji Mikami; Takafumi Aonishi; Hironori Yoshino; Chikara Ohta; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Commun., 2006)

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation. - Noriyuki Minegishi; Junichi Miyakoshi; Yuki Kuroda; Tadayoshi Katagiri; Yuki Fukuyama; Ryo Yamamoto; Masayuki Miyama; Kousuke Imamura; Hideo Hashimoto; Masahiko Yoshimoto (IEICE Trans. Electron., 2006)

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing. - Junichi Miyakoshi; Yuichiro Murachi; Tomokazu Ishihara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2006)

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. - Junichi Miyakoshi; Yuichiro Murachi; Tetsuro Matsuno; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Hiroshi Kawaguchi 001; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Kentaro Kawakami; Junichi Miyakoshi; Shinji Mikami; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture. - Kentaro Kawakami; Mitsuhiko Kuroda; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ASP-DAC, 2007)

A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Yasuhiro Morita; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISVLSI, 2007)

Multipath Routing using Isochronous Medium Access Control with Multi Wakeup Period for Wireless Sensor Networks. - Takashi Matsuda; Takafumi Aonishi; Takashi Takeuchi; Hiroshi Kawaguchi 001; Chikara Ohta; Masahiko Yoshimoto (ISWCS, 2007)

Delay Guarantee and Service Interval Optimization for HCCA in IEEE 802.11e WLANs. - Yuhi Higuchi; Augusto Foronda; Chikara Ohta; Masahiko Yoshimoto; Yoji Okada (WCNC, 2007)

Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE 802.11e WLANs. - Augusto Foronda; Yuhi Higuchi; Chikara Ohta; Masahiko Yoshimoto; Yoji Okada (IEICE Trans. Commun., 2007)

Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks. - Takashi Matsuda; Masumi Ichien; Hiroshi Kawaguchi 001; Chikara Ohta; Masahiko Yoshimoto (IEICE Trans. Commun., 2007)

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Yusuke Iguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Yusuke Iguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2007)

A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system. - Kazuo Miura; Hiroki Noguchi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (FPT, 2008)

An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding. - Kosuke Mizuno; Junichi Miyakoshi; Yuichiro Murachi; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Fang Yin; Jangchung Lee; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICECS, 2008)

A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. - Yuichiro Murachi; Kosuke Mizuno; Junichi Miyakoshi; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Fang Yin; Jangchung Lee; Tetsuya Kamino; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISCAS, 2008)

Quality of a Bit (QoB): A New Concept in Dependable SRAM. - Hidehiro Fujiwara; Shunsuke Okumura; Yusuke Iguchi; Hiroki Noguchi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2008)

Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks. - Shintaro Izumi; Takashi Takeuchi; Takashi Matsuda; Hiroshi Kawaguchi 001; Chikara Ohta; Masahiko Yoshimoto (IEICE Trans. Commun., 2008)

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. - Yuichiro Murachi; Yuki Fukuyama; Ryo Yamamoto; Junichi Miyakoshi; Hiroshi Kawaguchi 001; Hajime Ishihara; Masayuki Miyama; Yoshio Matsuda; Masahiko Yoshimoto (IEICE Trans. Electron., 2008)

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer. - Yuichiro Murachi; Junichi Miyakoshi; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Fang Yin; Jangchung Lee; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2008)

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Shunsuke Okumura; Yasuhiro Morita; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2008)

Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock. - Takashi Takeuchi; Yu Otake; Masumi Ichien; Akihiro Gion; Hiroshi Kawaguchi 001; Chikara Ohta; Masahiko Yoshimoto (IEICE Trans. Commun., 2008)

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. - Hidehiro Fujiwara; Koji Nii; Hiroki Noguchi; Junichi Miyakoshi; Yuichiro Murachi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system. - Tsuyoshi Fujinaga; Kazuo Miura; Hiroki Noguchi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (INTERSPEECH, 2009)

A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. - Shunsuke Okumura; Yusuke Iguchi; Shusuke Yoshimoto; Hidehiro Fujiwara; Hiroki Noguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2009)

An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks. - Hiroki Noguchi; Tomoya Takagi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (SiPS, 2009)

A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. - Hidehiro Fujiwara; Shunsuke Okumura; Yusuke Iguchi; Hiroki Noguchi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (VLSI Design, 2009)

A Dependable SRAM with 7T/14T Memory Cells. - Hidehiro Fujiwara; Shunsuke Okumura; Yusuke Iguchi; Hiroki Noguchi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2009)

A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks. - Takashi Takeuchi; Shinji Mikami; Hyeokjong Lee; Hiroshi Kawaguchi 001; Chikara Ohta; Masahiko Yoshimoto (IEICE Trans. Electron., 2009)

A 34.7-mW quad-core MIQP solver processor for robot control. - Hiroki Noguchi; Junichi Tani; Yusuke Shimai; Masanori Nishino; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2010)

7T SRAM enabling low-energy simultaneous block copy. - Shunsuke Okumura; Shusuke Yoshimoto; Kosuke Yamaguchi; Yohei Nakata; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2010)

Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. - Kosuke Mizuno; Hiroki Noguchi; Guangji He; Yosuke Terachi; Tetsuya Kamino; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (FPL, 2010)

Live demonstration: Intelligent ubiquitous sensor network for sound acquisition. - Koji Kugata; Tomoya Takagi; Hiroki Noguchi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ISCAS, 2010)

Intelligent ubiquitous sensor network for sound acquisition. - Koji Kugata; Tomoya Takagi; Hiroki Noguchi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ISCAS, 2010)

Parallel-processing VLSI architecture for mixed integer linear programming. - Hiroki Noguchi; Junichi Tani; Yusuke Shimai; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISCAS, 2010)

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. - Yohei Nakata; Shunsuke Okumura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2010)

A power-variation model for sensor node and the impact against life time of wireless sensor networks. - Takashi Matsuda; Takashi Takeuchi; Takefumi Aonishi; Masumi Ichien; Hiroshi Kawaguchi 001; Chikara Ohta; Masahiko Yoshimoto (IEICE Electron. Express, 2010)

A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design. - Shintaro Izumi; Takashi Takeuchi; Takashi Matsuda; Hyeokjong Lee; Toshihiro Konishi; Koh Tsuruda; Yasuharu Sakai; Hiroshi Kawaguchi 001; Chikara Ohta; Masahiko Yoshimoto (IEICE Trans. Electron., 2010)

A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition. - Guangji He; Takanobu Sugahara; Tsuyoshi Fujinaga; Yuki Miyamoto; Hiroki Noguchi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2011)

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. - Shunsuke Okumura; Yohei Nakata; Koji Yanagida; Yuki Kagiyama; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2011)

A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers. - Yohei Nakata; Yukihiro Takeuchi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (DSD, 2011)

Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units. - Yohei Nakata; Yasuhiro Ito; Yasuo Sugure; Shigeru Oho; Yusuke Takeuchi; Shunsuke Okumura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (DSN Workshops, 2011)

A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10-19. - Shunsuke Okumura; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ESSCIRC, 2011)

Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network. - Shintaro Izumi; Hiroki Noguchi; Tomoya Takagi; Koji Kugata; Shinpei Soda; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ICCCN, 2011)

256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V. - Jinwook Jung; Yohei Nakata; Shunsuke Okumura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICECS, 2011)

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. - Shusuke Yoshimoto; Takuro Amashita; D. Kozuwa; Taiga Takata; Masayoshi Yoshimura; Yusuke Matsunaga; Hiroto Yasuura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2011)

A 40-nm 640-µm2 45-dB opampless all-digital second-order MASH ΔΣ ADC. - Toshihiro Konishi; Hyeokjong Lee; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ISCAS, 2011)

0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM. - Hiroki Noguchi; Shunsuke Okumura; Tomoya Takagi; Koji Kugata; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ISQED, 2011)

Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. - Masahiro Yoshikawa; Shunsuke Okumura; Yohei Nakata; Yuki Kagiyama; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2011)

A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio. - Toshihiro Konishi; Shintaro Izumi; Koh Tsuruda; Hyeokjong Lee; Takashi Takeuchi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output. - Toshihiro Konishi; Hyeokjong Lee; Shintaro Izumi; Takashi Takeuchi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition. - Kosuke Mizuno; Hiroki Noguchi; Guangji He; Yosuke Terachi; Tetsuya Kamino; Tsuyoshi Fujinaga; Shintaro Izumi; Yasuo Ariki; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2011)

VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition. - Hiroki Noguchi; Kazuo Miura; Tsuyoshi Fujinaga; Takanobu Sugahara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2011)

7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. - Shunsuke Okumura; Yuki Kagiyama; Yohei Nakata; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Shunsuke Okumura; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Data-Intensive Sound Acquisition System with Large-scale Microphone Array. - Hiroki Noguchi; Tomoya Takagi; Koji Kugata; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (J. Inf. Process., 2011)

Implementing Virtual Agent as an Interface for Smart Home Voice Control. - Shinpei Soda; Masahide Nakamura; Shinsuke Matsumoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (APSEC, 2012)

Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores. - Koji Kugata; Shinpei Soda; Yohei Nakata; Shunsuke Okumura; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ARCS Workshops, 2012)

A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition. - Guangji He; Takanobu Sugahara; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2012)

Instantaneous Heart Rate detection using short-time autocorrelation for wearable healthcare systems. - Masanao Nakano; Toshihiro Konishi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (EMBC, 2012)

Handsfree Voice Interface for Home Network Service Using a Microphone Array Network. - Shinpei Soda; Masahide Nakamura; Shinsuke Matsumoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICNC, 2012)

Neutron-induced soft error rate estimation for SRAM using PHITS. - Shusuke Yoshimoto; Takuro Amashita; Masayoshi Yoshimura; Yusuke Matsunaga; Hiroto Yasuura; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2012)

A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping. - Toshihiro Konishi; Keisuke Okuno; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ISCAS, 2012)

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. - Shusuke Yoshimoto; Masaharu Terada; Youhei Umeki; Shunsuke Okumura; Atsushi Kawasumi; Toshikazu Suzuki; Shinichi Moriwaki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2012)

Bit error rate estimation in SRAM considering temperature fluctuation. - Yuki Kagiyama; Shunsuke Okumura; Koji Yanagida; Shusuke Yoshimoto; Yohei Nakata; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2012)

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. - Masaharu Terada; Shusuke Yoshimoto; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2012)

A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator. - Keisuke Okuno; Toshihiro Konishi; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (NEWCAS, 2012)

Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection. - Kosuke Mizuno; Yosuke Terachi; Kenta Takagi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (SiPS, 2012)

A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops. - Toshihiro Konishi; Keisuke Okuno; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (VLSIC, 2012)

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy. - Shunsuke Okumura; Yohei Nakata; Koji Yanagida; Yuki Kagiyama; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Electron. Express, 2012)

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Electron. Express, 2012)

Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes. - Takashi Matsuda; Shintaro Izumi; Yasuharu Sakai; Takashi Takeuchi; Hidehiro Fujiwara; Hiroshi Kawaguchi 001; Chikara Ohta; Masahiko Yoshimoto (IEICE Trans. Commun., 2012)

A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing. - Yohei Nakata; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2012)

A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. - Shunsuke Okumura; Hidehiro Fujiwara; Kosuke Yamaguchi; Shusuke Yoshimoto; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Electron., 2012)

A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. - Shunsuke Okumura; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. - Shusuke Yoshimoto; Takuro Amashita; Shunsuke Okumura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2012)

Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. - Shusuke Yoshimoto; Takuro Amashita; Shunsuke Okumura; Koji Nii; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2012)

0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. - Yohei Nakata; Shunsuke Okumura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition. - Guangji He; Takanobu Sugahara; Yuki Miyamoto; Tsuyoshi Fujinaga; Hiroki Noguchi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. - Shunsuke Okumura; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ASP-DAC, 2013)

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ASP-DAC, 2013)

Low-power hardware implementation of noise tolerant heart rate extractor for a wearable monitoring system. - Shintaro Izumi; Masanao Nakano; Ken Yamashita; Takahide Fujii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (BIBE, 2013)

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. - Shusuke Yoshimoto; Shinji Miyano; Makoto Takamiya; Hirofumi Shinohara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2013)

Noise-tolerant instantaneous heart rate and R-peak detection using short-term autocorrelation for wearable healthcare systems. - Takahide Fujii; Masanao Nakano; Ken Yamashita; Toshihiro Konishi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (EMBC, 2013)

A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system. - Shintaro Izumi; Ken Yamashita; Masanao Nakano; Toshihiro Konishi; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori; Hiroshi Nakajima; Toshikazu Shiga; Masahiko Yoshimoto (ESSCIRC, 2013)

A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection. - Kenta Takagi; Kosuke Mizuno; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICASSP, 2013)

Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags. - Jinwook Jung; Yohei Nakata; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ISQED, 2013)

Temperature compensation using least mean squares for fast settling all-digital phase-locked loop. - Keisuke Okuno; Shintaro Izumi; Toshihiro Konishi; Song Dae-Woo; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (NEWCAS, 2013)

A 38 μA wearable biosignal monitoring system with near field communication. - Ken Yamashita; Shintaro Izumi; Masanao Nakano; Takahide Fujii; Toshihiro Konishi; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori; Hiroshi Nakajima; Toshikazu Shiga; et al. (NEWCAS, 2013)

A 40-NM 54-MW 3×-real-time VLSI processor for 60-kWord continuous speech recognition. - Guangji He; Yuki Miyamoto; Kumpei Matsuda; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (SiPS, 2013)

A 168-mW 2.4X-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI. - Guangji He; Takanobu Sugahara; Yuki Miyamoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2013)

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM. - Jinwook Jung; Yohei Nakata; Shunsuke Okumura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2013)

An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter. - Toshihiro Konishi; Keisuke Okuno; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops. - Toshihiro Konishi; Keisuke Okuno; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Electron., 2013)

A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video. - Kosuke Mizuno; Kenta Takagi; Yosuke Terachi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2013)

Foreword. - Masahiko Yoshimoto (IEICE Trans. Electron., 2013)

Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. - Shusuke Yoshimoto; Shunsuke Okumura; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

An FPGA Implementation of a HOG-based Object Detection Processor. - Kosuke Mizuno; Yosuke Terachi; Kenta Takagi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. - Go Matsukawa; Yohei Nakata; Yuta Kimi; Yasuo Sugure; Masafumi Shimozawa; Shigeru Oho; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ARCS Workshops, 2014)

Normally-off technologies for healthcare appliance. - Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto; Yoshikazu Fujimori (ASP-DAC, 2014)

A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability. - Hiromitsu Kimura; Takaaki Fuchikami; Kyoji Marumoto; Yoshikazu Fujimori; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (A-SSCC, 2014)

A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems. - Shintaro Izumi; Ken Yamashita; Masanao Nakano; Tomoki Nakagawa; Yuki Kitahara; Koji Yanagida; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori; et al. (BioCAS, 2014)

Noise tolerant QRS detection using template matching with short-term autocorrelation. - Yozaburo Nakai; Shintaro Izumi; Masanao Nakano; Ken Yamashita; Takahide Fujii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (EMBC, 2014)

An 8-bit I/O-sized ADC with second-order TDC and MOM capacitor voltage-to-time converter. - Keisuke Okuno; Toshihiro Konishi; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (ICECS, 2014)

A 2.23 ps RMS jitter 3 μs fast settling ADPLL using temperature compensation PLL controller. - Keisuke Okuno; Kana Masaki; Shintaro Izumi; Toshihiro Konishi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICECS, 2014)

A 6T-4C shadow memory using plate line and word line boosting. - Tomoki Nakagawa; Shintaro Izumi; Shusuke Yoshimoto; Koji Yanagida; Yuki Kitahara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISCAS, 2014)

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (ISQED, 2014)

A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI. - Guangji He; Yuki Miyamoto; Kumpei Matsuda; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Electron. Express, 2014)

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (IEICE Trans. Electron., 2014)

STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell. - Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI. - Kenta Takagi; Kotaro Tanaka; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (J. Signal Process. Syst., 2014)

A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems. - Yozaburo Nakai; Shintaro Izumi; Ken Yamashita; Masanao Nakano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ASP-DAC, 2015)

A negative-resistance sense amplifier for low-voltage operating STT-MRAM. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (ASP-DAC, 2015)

Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path. - Yuta Kimi; Go Matsukawa; Shuhei Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ATS, 2015)

A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2015)

Large displacement haptic stimulus actuator using piezoelectric pump for wearable devices. - Taisuke Kodama; Shintaro Izumi; Kana Masaki; Hiroshi Kawaguchi 001; Kazusuke Maenaka; Masahiko Yoshimoto (EMBC, 2015)

Non-contact and noise tolerant heart rate monitoring using microwave doppler sensor and range imagery. - Daichi Matsunaga; Shintaro Izumi; Keisuke Okuno; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (EMBC, 2015)

Physical activity group classification algorithm using triaxial acceleration and heart rate. - Motofumi Nakanishi; Shintaro Izumi; Sho Nagayoshi; Hironori Sato; Hiroshi Kawaguchi 001; Masahiko Yoshimoto; Takafumi Ando; Satoshi Nakae; Chiyoko Usui; Tomoko Aoyama; Shigeho Tanaka (EMBC, 2015)

A more acceptable endoluminal implantation for remotely monitoring ingestible sensors anchored to the stomach wall. - Hidetoshi Ohta; Shintaro Izumi; Masahiko Yoshimoto (EMBC, 2015)

An accurate soft error propagation analysis technique considering temporal masking disablement. - Yuta Kimi; Go Matsukawa; Shuhei Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2015)

A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. - Tomoki Nakagawa; Shintaro Izumi; Koji Yanagida; Yuki Kitahara; Shusuke Yoshimoto; Yohei Umeki; Haruki Mori; Hiroto Kitahara; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; et al. (ISCAS, 2015)

A ferroelectric-based non-volatile flip-flop for wearable healthcare systems. - Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto; Hiromitsu Kimura; Takaaki Fuchikami; Kyoji Marumoto; Yoshikazu Fujimori (NVMTS, 2015)

Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems. - Shintaro Izumi; Masanao Nakano; Ken Yamashita; Yozaburo Nakai; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Inf. Syst., 2015)

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. - Go Matsukawa; Yohei Nakata; Yasuo Sugure; Shigeru Oho; Yuta Kimi; Masafumi Shimozawa; Shuhei Yoshida; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2015)

A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm. - Keisuke Okuno; Shintaro Izumi; Kana Masaki; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter. - Keisuke Okuno; Toshihiro Konishi; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Electron., 2015)

Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators. - Keisuke Okuno; Toshihiro Konishi; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A Wearable Healthcare System With a 13.7 µ A Noise Tolerant ECG Processor. - Shintaro Izumi; Ken Yamashita; Masanao Nakano; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori; Hiroshi Nakajima; Toshikazu Shiga; Masahiko Yoshimoto (IEEE Trans. Biomed. Circuits Syst., 2015)

Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector. - Shintaro Izumi; Ken Yamashita; Masanao Nakano; Shusuke Yoshimoto; Tomoki Nakagawa; Yozaburo Nakai; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori; Hiroshi Nakajima; et al. (IEEE Trans. Biomed. Circuits Syst., 2015)

Capacitively coupled ECG sensor using a single electrode with adaptive power-line noise cancellation. - Yuta Kawamoto; Shintaro Izumi; Yoshito Tanaka; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (BHI, 2016)

Non-contact Instantaneous Heart Rate Monitoring Using Microwave Doppler Sensor and Time-Frequency Domain Analysis. - Daichi Matsunaga; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (BIBE, 2016)

Adaptive noise cancellation method for capacitively coupled ECG sensor using single insulated electrode. - Yoshito Tanaka; Shintaro Izumi; Yuta Kawamoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (BioCAS, 2016)

Swallowable sensing device for long-term gastrointestinal tract monitoring. - Ryota Nakamura; Shintaro Izumi; Hiroshi Kawaguchi 001; Hidetoshi Ohta; Masahiko Yoshimoto (EMBC, 2016)

Low-power metabolic equivalents estimation algorithm using adaptive acceleration sampling. - Mio Tsukahara; Motofumi Nakanishi; Shintaro Izumi; Yozaburo Nakai; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (EMBC, 2016)

An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICECS, 2016)

A 15-μA metabolic equivalents monitoring system using adaptive acceleration sampling and normally off computing. - Mio Tsukahara; Shintaro Izumi; Motofumi Nakanishi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori (ICECS, 2016)

An soft error propagation analysis considering logical masking effect on re-convergent path. - Shuhei Yoshida; Go Matsukawa; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2016)

Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path. - Go Matsukawa; Yuta Kimi; Shuhei Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. - Haruki Mori; Yohei Umeki; Shusuke Yoshimoto; Shintaro Izumi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2016)

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (IPSJ Trans. Syst. LSI Des. Methodol., 2016)

A 19-μA metabolic equivalents monitoring SoC using adaptive sampling. - Mio Tsukahara; Shintaro Izumi; Motofumi Nakanishi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori (ASP-DAC, 2017)

Wearable pulse wave velocity sensor using flexible piezoelectric film array. - Takumi Katsuura; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Shusuke Yoshimoto; Tsuyoshi Sekitani (BioCAS, 2017)

Capacitively coupled ECG sensor system with digitally assisted noise cancellation for wearable application. - Yuki Nagasato; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (BioCAS, 2017)

Non-contact biometric identification and authentication using microwave Doppler sensor. - Takaaki Okano; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (BioCAS, 2017)

A swallowable sensing device platform with wireless power feeding and chemical reaction actuator. - Ryota Nakamura; Shintaro Izumi; Hiroshi Kawaguchi 001; Hidetoshi Ohta; Masahiko Yoshimoto (EMBC, 2017)

A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning. - Haruki Mori; Tetsuya Youkawa; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Atsuki Inoue (MLSP, 2017)

FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature. - Yuri Nishizumi; Go Matsukawa; Koichi Kajihara; Taisuke Kodama; Shintaro Izumi; Hiroshi Kawaguchi 001; Chikako Nakanishi; Toshio Goto; Takeo Kato; Masahiko Yoshimoto (SiPS, 2017)

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video. - Go Matsukawa; Taisuke Kodama; Yuri Nishizumi; Koichi Kajihara; Chikako Nakanishi; Shintaro Izumi; Hiroshi Kawaguchi 001; Toshio Goto; Takeo Kato; Masahiko Yoshimoto (IEICE Electron. Express, 2017)

Delayed Weight Update for Faster Convergence in Data-Parallel Deep Learning. - Tetsuya Youkawa; Haruki Mori; Yuki Miyauchi; Kazuki Yamada; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (GlobalSIP, 2018)

Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth. - Yuki Miyauchi; Haruki Mori; Tetsuya Youkawa; Kazuki Yamada; Shintato Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Atsuki Inoue (ICECS, 2018)

28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning. - Haruki Mori; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICECS, 2018)

Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring. - Yuki Nishikawa; Shintaro Izumi; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISCAS, 2018)

Hardware Implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis. - Koichi Kajihara; Shintaro Izumi; Seiya Yoshida; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (SiPS, 2018)

Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning. - Kazuki Yamada; Haruki Mori; Tetsuya Youkawa; Yuki Miyauchi; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (SiPS, 2018)

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668]. - Go Matsukawa; Taisuke Kodama; Yuri Nishizumi; Koichi Kajihara; Chikako Nakanishi; Shintaro Izumi; Hiroshi Kawaguchi 001; Toshio Goto; Takeo Kato; Masahiko Yoshimoto (IEICE Electron. Express, 2018)

A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate. - Motofumi Nakanishi; Shintaro Izumi; Mio Tsukahara; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori; Masahiko Yoshimoto (IEICE Trans. Electron., 2018)

An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. - Yuji Yano; Seiya Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Tetsuya Hirose; Masaya Miyahara; Teruki Someya; Kenichi Okada 001; Ippei Akita; Yoshihiko Kurui; Hideyuki Tomizawa; Masahiko Yoshimoto (A-SSCC, 2019)

A Heartbeat Interval Error Compensation Method Using Multiple Linear Regression for Photoplethysmography Sensors. - Seiya Yoshida; Shintaro Izumi; Yuki Nishikawa; Kento Watanabe; Kana Sasai; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (BioCAS, 2019)

A Low-Power Photoplethysmography Sensor using Correlated Double Sampling and Reference Readout Circuit. - Kana Sasai; Shintaro Izumi; Kento Watanabe; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE SENSORS, 2019)

Non-Contact Instantaneous Heart Rate Extraction System Using 24-GHz Microwave Doppler Sensor. - Shintaro Izumi; Takaaki Okano; Daichi Matsunaga; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Commun., 2019)

Recent Progress of Biomedical Processor SoC for Wearable Healthcare Application: A Review. - Masahiko Yoshimoto; Shintaro Izumi (IEICE Trans. Electron., 2019)

Low-Noise Photoplethysmography Sensor Using Correlated Double Sampling for Heartbeat Interval Acquisition. - Kento Watanabe; Shintaro Izumi; Kana Sasai; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Biomed. Circuits Syst., 2019)

A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Energy-Efficient Spectral Analysis Method Using Autoregressive Model-Based Approach for Internet of Things. - Seiya Yoshida; Shintaro Izumi; Koichi Kajihara; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare. - Takaaki Okano; Shintaro Izumi; Takumi Katsuura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (J. Signal Process. Syst., 2019)

A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection. - Reiya Kawamoto; Masakazu Taichi; Masaya Kabuto; Daisuke Watanabe; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (AICAS, 2020)

An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. - Daisuke Watanabe; Yuji Yano; Shintaro Izumi; Hiroshi Kawaguchi 001; Kiyoshi Takeuchi; Toshiro Hiramoto; Shoichi Iwai; Masami Murakata; Masahiko Yoshimoto (AICAS, 2020)

Heartbeat Interval Error Compensation Method for Low Sampling Rates Photoplethysmography Sensors. - Kento Watanabe; Shintaro Izumi; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Commun., 2020)

A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations. - Reiya Kawamoto; Masakazu Taichi; Masaya Kabuto; Daisuke Watanabe; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Go Matsukawa; Toshio Goto; Motoshi Kojima (IEEE J. Sel. Top. Signal Process., 2020)