A 1 kbit Josephson random access memory using variable threshold cells. - Itaru Kurosawa; Hiroshi Nakagawa; Shin Kosaka; Masahiro Aoyagi; Susumu Takada (IEEE J. Solid State Circuits, 1989)

A Josephson 4 bit RALU for a prototype computer. - Hiroshi Nakagawa; Shin Kosaka; Hiroki Kawamura; Itaru Kurosawa; Masahiro Aoyagi; Youichi Hamazaki; Yoshikuni Okada; Susumu Takada (IEEE J. Solid State Circuits, 1989)

A Josephson 10-b instruction 128-word ROM unit. - Masahiro Aoyagi; Hiroshi Nakagawa; Itaru Kurosawa; Shin Kosaka; Yoshikuni Okada; Youichi Hamazaki; Susumu Takada (IEEE J. Solid State Circuits, 1990)

A fully operational 1 kb variable threshold Josephson RAM. - Itaru Kurosawa; Hiroshi Nakagawa; Masahiro Aoyagi; Shin Kosaka; Susumu Takada (IEEE J. Solid State Circuits, 1991)

Band-Stop Filter Effect of Power/Ground Plane on Through-Hole Signal Via in Multilayer PCB. - Junso Pak; Masahiro Aoyagi; Katsuya Kikuchi; Joungho Kim (IEICE Trans. Electron., 2006)

Chemical flip-chip bonding method for fabricating 10-µm-pad-pitch interconnect. - Yasuhiro Yamaji; Tokihiko Yokoshima; Katsuya Kikuchi; Hiroshi Nakagawa; Masahiro Aoyagi (IEICE Electron. Express, 2008)

Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates. - Katsuya Kikuchi; Koichi Takemura; Chihiro Ueda; Osamu Shimada; Toshio Gomyo; Yukiharu Takeuchi; Toshikazu Okubo; Kazuhiro Baba; Masahiro Aoyagi; Toshio Sudo; Kanji Otsuka (3DIC, 2009)

SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integration. - Koichi Takemura; Katsuya Kikuchi; Chihiro Ueda; Kazuhiro Baba; Masahiro Aoyagi; Kanji Otsuka (3DIC, 2009)

Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration. - Fumiki Kato; Katsuya Kikuchi; Hiroshi Nakagawa; Masahiro Aoyagi (3DIC, 2011)

PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. - Katsuya Kikuchi; Chihiro Ueda; Fumiaki Fujii; Yutaka Akiyama; Naoya Watanabe; Yasuhiro Kitamura; Toshio Gomyo; Toshikazu Okubo; Tetsuya Koyama; Tadashi Kamada; Masahiro Aoyagi; Kanji Otsuka (3DIC, 2011)

Damage evaluation of wet-chemical silicon-wafer thinning process. - Naoya Watanabe; Takumi Miyazaki; Masahiro Aoyagi; Kazuhiro Yoshikawa (3DIC, 2011)

COOL interconnect low power interconnection technology for scalable 3D LSI design. - Marco Chacin; Hiroyuki Uchida; Michiya Hagimoto; Takashi Miyazaki; Takeshi Ohkawa; Rimon Ikeno; Yukoh Matsumoto; Fumito Imura; Motohiro Suzuki; Katsuya Kikuchi; Hiroshi Nakagawa; Masahiro Aoyagi (COOL Chips, 2011)

Cool System scalable 3-D stacked heterogeneous Multi-Core / Multi-Chip architecture for ultra low-power digital TV applications. - Yukoh Matsumoto; Tomoyuki Morimoto; Michiya Hagimoto; Hiroyuki Uchida; Nobuyuki Hikichi; Fumito Imura; Hiroshi Nakagawa; Masahiro Aoyagi (COOL Chips, 2012)

New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. - Masahiro Aoyagi; Naoya Watanabe; Motohiro Suzuki; Katsuya Kikuchi; Shunsuke Nemoto; Noriaki Arima; Misaki Ishizuka; Koji Suzuki; Toshio Shiomi (3DIC, 2013)

Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging. - Katsuya Kikuchi; Fumiki Kato; Shunsuke Nemoto; Hiroshi Nakagawa; Masahiro Aoyagi; Youtaro Yasu; Kohji Koshiji (3DIC, 2013)

Special session 4C: Hot topic 3D-IC design and test. - Jin-Fu Li 001; Cheng-Wen Wu; Masahiro Aoyagi; Meng-Fan Marvin Chang; Ding-Ming Kwai (VTS, 2013)

Substrate monitoring system for inspecting defects in TSV-based data buses. - Yuuki Araga; Kikuchi Katsuya; Masahiro Aoyagi (3DIC, 2014)

Analysis of thermal stress distribution for TSV with novel structure. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (3DIC, 2014)

Ultrawideband ultralow PDN impedance of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology for 3-D integrated LSI system. - Katsuya Kikuchi; Masahiro Aoyagi; Masaaki Ujiie; Shinya Takayama (3DIC, 2014)

Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. - Bui Thanh Tung 001; Xiaojin Cheng; Naoya Watanabe; Fumiki Kato; Katsuya Kikuchi; Masahiro Aoyagi (3DIC, 2014)

Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal. - Naoya Watanabe; Masahiro Aoyagi; Daisuke Katagawa; Tsubasa Bandoh; Takahiko Mitsui; Eiichi Yamamoto (3DIC, 2014)

Guard-ring monitoring system for inspecting defects in TSV-based data buses. - Yuuki Araga; Kikuchi Katsuya; Masahiro Aoyagi (3DIC, 2015)

Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. - Tung Thanh Bui 001; Naoya Watanabe; Masahiro Aoyagi; Katsuya Kikuchi (3DIC, 2015)

Investigation of effects of metalization on heat spreading in bump-bonded 3D systems. - Samson Melamed; Katsuya Kikuchi; Masahiro Aoyagi (3DIC, 2015)

Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit. - Samson Melamed; Fumito Imura; Hiroshi Nakagawa; Katsuya Kikuchi; Michiya Hagimoto; Yukoh Matsumoto; Masahiro Aoyagi (Microelectron. J., 2015)

3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions. - Makoto Motoyoshi; Kohki Yanagimura; Taikoh Fushimi; Junichi Takanohashi; Mariappan Murugesan; Masahiro Aoyagi; Mitsumasa Koyanagi (3DIC, 2016)

Wet cleaning process for high-yield via-last TSV formation. - Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi; Hidekazu Kikuchi; Azusa Yanagisawa; Akio Nakamura (3DIC, 2016)

Two-axis tilt angle detection based on dielectric liquid capacitive sensor. - Tiep Dang Dinh; Tung Thanh Bui 001; Tuan Vu Quoc; Thinh Pham Quoc; Masahiro Aoyagi; My Bui Ngoc; Trinh Chu Duc (IEEE SENSORS, 2016)

Fabrication and stress analysis of annular-trench-isolated TSV. - Wei Feng; Tung Thanh Bui 001; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (Microelectron. Reliab., 2016)

Validation of TSV thermo-mechanical simulation by stress measurement. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (Microelectron. Reliab., 2016)

Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. - Samson Melamed; Naoya Watanabe; Shunsuke Nemoto; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (Microelectron. Reliab., 2016)

Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus. - Takeshi Ohkawa; Kanemitsu Ootsu; Takashi Yokota; Katsuya Kikuchi; Masahiro Aoyagi (MCSoC, 2017)

Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. - Samson Melamed; Naoya Watanabe; Shunsuke Nemoto; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (Microelectron. Reliab., 2017)

Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs. - Yuuki Araga; Kikuchi Katsuya; Masahiro Aoyagi (3DIC, 2019)

Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (3DIC, 2019)

FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System. - Takeshi Ohkawa; Masahiro Aoyagi (COOL CHIPS, 2023)