A distributed shared memory multiprocessor ASURA: memory and cache architecture. - Shin-ichiro Mori; Hideki Saito 001; Masahiro Goshima; Mamoru Yanagihara; Takashi Tanaka; David Fraser; Kazuki Joe; Hiroyuki Nitta; Shinji Tomita (SC, 1993)

A proposal of self-cleanup cache. - Shin-ichiro Mori; Masahiro Goshima; Hiroshi Nakashima; Shinji Tomita (PACT, 1995)

Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis. - Kazuhiko Ohno; Masahiko Ikawa; Masahiro Goshima; Shin-ichiro Mori; Hiroshi Nakashima; Shinji Tomita (ASIAN, 1997)

Improvement of message communication in concurrent logic language. - Kazuhiko Ohno; Masahiko Ikawa; Shin-ichiro Mori; Hiroshi Nakashima; Shinji Tomita; Masahiro Goshima (PASCO, 1997)

Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPAR. - Shin-ya Goto; Atsushi Kubota; Toshihiko Tanaka; Masahiro Goshima; Shin-ichiro Mori; Hiroshi Nakashima; Shinji Tomita (IEEE PACT, 1998)

A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR. - Atsushi Kubota; Shogo Tatsumi; Toshihiko Tanaka; Masahiro Goshima; Shin-ichiro Mori; Hiroshi Nakashima; Shinji Tomita (Int. J. Parallel Program., 1999)

A high-speed dynamic instruction scheduling scheme for superscalar processors. - Masahiro Goshima; Kengo Nishino; Toshiaki Kitamura; Yasuhiko Nakashima; Shinji Tomita; Shin-ichiro Mori (MICRO, 2001)

Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing. - Motohiro Takayama; Yuki Shinomoto; Masahiro Goshima; Shin-ichiro Mori; Yasuhiko Nakashima; Shinji Tomita (PDPTA, 2004)

Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. - Luong Dinh Hung; Masahiro Goshima; Shuichi Sakai (ICCD, 2005)

SEVA: A Soft-Error- and Variation-Aware Cache Architecture. - Luong Dinh Hung; Masahiro Goshima; Shuichi Sakai (PRDC, 2006)

Base Address Recognition with Data Flow Tracking for Injection Attack Detection. - Satoshi Katsunuma; Hiroyuki Kurita; Ryota Shioya; Kazuto Shimizu; Hidetsugu Irie; Masahiro Goshima; Shuichi Sakai (PRDC, 2006)

Utilization of SECDED for soft error and variation-induced defect tolerance in caches. - Luong Dinh Hung; Hidetsugu Irie; Masahiro Goshima; Shuichi Sakai (DATE, 2007)

Preventing timing errors on register writes: mechanisms of detections and recoveries. - Hidetsugu Irie; Ken Sugimoto; Masahiro Goshima; Shuichi Sakai (SIGARCH Comput. Archit. News, 2007)

Low-Complexity Bypass Network Using Small RAM. - Shinobu Miwa; Hironori Ichibayashi; Hidetsugu Irie; Masahiro Goshima; Hironori Nakajo; Shinji Tomita (CDES, 2008)

Ultra Dependable Processor. - Shuichi Sakai; Masahiro Goshima; Hidetsugu Irie (IEICE Trans. Electron., 2008)

String-Wise Information Flow Tracking against Script Injection Attacks. - Kunbo Li; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (PRDC, 2009)

Register Cache System Not for Latency Reduction Purpose. - Ryota Shioya; Kazuo Horio; Masahiro Goshima; Shuichi Sakai (MICRO, 2010)

Low-Overhead Architecture for Security Tag. - Ryota Shioya; Daewung Kim; Kazuo Horio; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2011)

Register Indirect Jump Target Forwarding. - Ryota Shioya; Naruki Kurata; Takashi Toyoshima; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2013)

A cloud architecture for protecting guest's information from malicious operators with memory management. - Koki Murakami; Tsuyoshi Yamada; Rie Shigetomi Yamaguchi; Masahiro Goshima; Shuichi Sakai (CODASPY, 2014)

A Front-End Execution Architecture for High Energy Efficiency. - Ryota Shioya; Masahiro Goshima; Hideki Ando (MICRO, 2014)

Address Order Violation Detection with Parallel Counting Bloom Filters. - Naruki Kurata; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Electron., 2015)

An Inductive Method to Select Simulation Points. - Minseong Choi; Takashi Fukuda; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2016)

FXA: Executing Instructions in Front-End for Energy Efficiency. - Ryota Shioya; Ryo Takami; Masahiro Goshima; Hideki Ando (IEICE Trans. Inf. Syst., 2016)

Initial study of a phase-aware scheduling for hardware transactional memory. - Tomoki Tajimi; Anju Hirota; Ryota Shioya; Masahiro Goshima; Tomoaki Tsumura (PACRIM, 2017)

Applying Razor Flip-Flops to SRAM Read Circuits. - Ushio Jimbo; Junji Yamada; Ryota Shioya; Masahiro Goshima (IEICE Trans. Electron., 2017)

Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Electron., 2017)

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2017)

A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode. - Yasumasa Chidai; Kojiro Izuoka; Ryota Shioya; Masahiro Goshima; Hideki Ando (ARCS, 2018)

Application of Timing Fault Detection to Rocket Core on FPGA. - Ushio Jimbo; Ryota Shioya; Masahiro Goshima (CANDAR Workshops, 2018)

An Analysis and a Solution of False Conflicts for Hardware Transactional Memory. - Yuki Futamase; Masaki Hayashi; Tomoki Tajimi; Ryota Shioya; Masahiro Goshima; Tomoaki Tsumura (ICECS, 2018)

Isolation-Safe Speculative Access Control for Hardware Transactional Memory. - Tomoki Tajimi; Masaki Hayashi; Yuki Futamase; Ryota Shioya; Masahiro Goshima; Tomoaki Tsumura (ICECS, 2018)

Bank-Aware Instruction Scheduler for a Multibanked Register File. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (J. Inf. Process., 2018)

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. - Susumu Mashimo; Koji Inoue; Ryota Shioya; Akifumi Fujita; Reoma Matsuo; Seiya Akaki; Akifumi Fukuda; Toru Koizumi 001; Junichiro Kadomoto; Hidetsugu Irie; Masahiro Goshima (FPT, 2019)

Out-of-Step Pipeline for Gather/Scatter Instructions. - Yi Ge; Katsuhiro Yoda; Makiko Ito; Toshiyuki Ichiba; Takahide Yoshikawa; Ryota Shioya; Masahiro Goshima (DATE, 2023)