A 400 K-transistor CMOS sea-of-gates array with continuous track allocation. - Masatomi Okabe; Yoshihiro Okuno; Takahiko Arakawa; Ichiro Tomioka; Takio Ohno; Tomoyoshi Noda; Masahiro Hatanaka; Yoichi Kuramitsu (IEEE J. Solid State Circuits, 1989)

A 24-b 50-ns digital image signal processor. - Shin-ichi Nakagawa; Hideyuki Terane; Tetsuya Matsumura; Hiroshi Segawa; Masahiko Yoshimoto; Hirofumi Shinohara; Shuichi Kato; Masahiro Hatanaka; Hideo Ohira; Yoshiaki Kato; Mamoru Iwatsuki; Kinya Tabuchi; et al. (IEEE J. Solid State Circuits, 1990)

A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates. - Toshiaki Hanibuchi; Masahiro Ueda; Keiichi Higashitani; Masahiro Hatanaka; Koichiro Mashiko; Akiharu Tada (IEEE J. Solid State Circuits, 1991)

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy. - Atsushi Ohba; Shigeki Ohbayashi; Toru Shiomi; Satoshi Takano; Kenji Anami; Hiroki Honda; Yoshiyuki Ishigaki; Masahiro Hatanaka; Shigeo Nagao; Shimpei Kayano (IEEE J. Solid State Circuits, 1991)

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. - Shin'ichi Kobayashi; Hiroaki Nakai; Yuichi Kunori; Takeshi Nakayama; Yoshikazu Miyawaki; Yasushi Terada; Hiroshi Onoda; Natsuo Ajika; Masahiro Hatanaka; Hirokazu Miyoshi; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1994)