A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data Bandwidth. - Chih Tseng; Jae-Hyeong Kim; Suzanne Chen; Mu-Hsiang Huang; Chungji Lu; Ikio Hashiguchi; Yoshifumi Miyazima; Masahiro Ichihashi; Kentaro Maki; Katsuya Nakashima; Patrick Chuang (ISSCC, 2006)

A Low-Power and GHz-Band LC-DCO Directly Drives 10mm On-Chip Clock Distribution Line in 0.18µm CMOS. - Masahiro Ichihashi; Haruichi Kanaya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

3.3-mA 2.8-GHz bufferless LC oscillator directly driving a 10-mm on-chip clock distribution line. - Masahiro Ichihashi; Shogo Harada; Haruichi Kanaya (IEICE Electron. Express, 2019)