Programming for Parallel Pattern Generators. - M. Kanzaki; Masahiro Ishida (ITC, 1991)

An Efficient Method for Compressing Test Data. - Takahiro J. Yamaguchi; Masahiro Ishida; Marco Tilgner; Dong Sam Ha (ITC, 1997)

COMPACT: A Hybrid Method for Compressing Test Data. - Masahiro Ishida; Dong Sam Ha; Takahiro J. Yamaguchi (VTS, 1998)

Jitter measurements of a PowerPCTM microprocessor using an analytic signal method. - Takahiro J. Yamaguchi; Mani Soma; David Halter; Jim Nissen; Rajesh Raina; Masahiro Ishida; Toshifumi Watanabe (ITC, 2000)

Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method. - Takahiro J. Yamaguchi; Masahiro Ishida; Mani Soma; Toshifumi Watanabe; Tadahiro Ohmi (VTS, 2000)

Testing clock distribution circuits using an analytic signal method. - Takahiro J. Yamaguchi; Mani Soma; Jim Nissen; David Halter; Rajesh Raina; Masahiro Ishida (ITC, 2001)

A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. - Takahiro J. Yamaguchi; Masahiro Ishida; Mani Soma; David Halter; Rajesh Raina; Jim Nissen (VTS, 2001)

Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices. - Masahiro Ishida; Takahiro J. Yamaguchi; Mani Soma; Hirobumi Musha (Asian Test Symposium, 2002)

A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter. - Takahiro J. Yamaguchi; Mani Soma; Masahiro Ishida; Hirobumi Musha; Louis Malarsie (ITC, 2002)

Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division. - Takahiro J. Yamaguchi; Masahiro Ishida; Mani Soma; Louis Malarsie; Hirobumi Musha (VTS, 2002)

A Method for Compressing Test Data Based on Burrows-Wheeler Transformation. - Takahiro J. Yamaguchi; Dong Sam Ha; Masahiro Ishida; Tadahiro Ohmi (IEEE Trans. Computers, 2002)

Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements. - Takahiro J. Yamaguchi; Mani Soma; Masahiro Ishida; Makoto Kurosawa; Hirobumi Musha (ITC, 2003)

Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division. - Takahiro J. Yamaguchi; Masahiro Ishida; Mani Soma; Louis Malarsie; Hirobumi Musha (J. Electron. Test., 2003)

Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method. - Takahiro J. Yamaguchi; Mani Soma; Masahiro Ishida; Toshifumi Watanabe; Tadahiro Ohmi (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems. - Takahiro J. Yamaguchi; Masahiro Ishida; Kiyotaka Ichiyama; Mani Soma; Christian Krawinkel; Katsuaki Ohsawa; Masao Sugai (ITC, 2004)

Skew measurements in clock distribution circuits using an analytic signal method. - Takahiro J. Yamaguchi; Mani Soma; Jim Nissen; David Halter; Rajesh Raina; Masahiro Ishida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A wideband low-noise ATE-based method for measuring jitter in GHz signals. - Takahiro J. Yamaguchi; Masahiro Ishida; Mani Soma (ITC, 2005)

A Real-Time Delta-Time-to-Voltage Converter for Clock Jitter Measurement. - Kiyotaka Ichiyama; Masahiro Ishida; Takahiro J. Yamaguchi; Mani Soma (ITC, 2006)

A Study of Per-Pin Timing Jitter Scope. - Takahiro J. Yamaguchi; Satoshi Iwamoto; Masahiro Ishida; Mani Soma (ITC, 2006)

Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter. - Kiyotaka Ichiyama; Masahiro Ishida; Takahiro J. Yamaguchi; Mani Soma (CICC, 2007)

An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter. - Kiyotaka Ichiyama; Masahiro Ishida; Takahiro J. Yamaguchi; Mani Soma (ISCAS, 2007)

Data jitter measurement using a delta-time-to-voltage converter method. - Kiyotaka Ichiyama; Masahiro Ishida; Takahiro J. Yamaguchi; Mani Soma (ITC, 2007)

An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test time. - Takahiro J. Yamaguchi; H. X. Hou; Koji Takayama; Dave Armstrong; Masahiro Ishida; Mani Soma (ITC, 2007)

Total Jitter Measurement for Testing HSIO Integrated SoCs. - Takahiro J. Yamaguchi; Masahiro Ishida (ATS, 2008)

A New Method for Measuring Aperture Jitter in ADC Output and Its Application to ENOB Testing. - Takahiro J. Yamaguchi; Masayuki Kawabata; Mani Soma; Masahiro Ishida; K. Sawami; Koichiro Uekusa (ITC, 2008)

A robust method for identifying a deterministic jitter model in a total jitter distribution. - Takahiro J. Yamaguchi; Kiyotaka Ichiyama; X. H. Hou; Masahiro Ishida (ITC, 2009)

Real-time testing method for 16 Gbps 4-PAM signal interface. - Masahiro Ishida; Kiyotaka Ichiyama; Daisuke Watanabe; Masayuki Kawabata; Toshiyuki Okayasu (ITC, 2011)

Post-Silicon Jitter Measurements. - Kiichi Niitsu; Takahiro J. Yamaguchi; Masahiro Ishida; Haruo Kobayashi 001 (Asian Test Symposium, 2012)

Power integrity control of ATE for emulating power supply fluctuations on customer environment. - Masahiro Ishida; Toru Nakura; Toshiyuki Kikkawa; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (ITC, 2012)

Marker based camera pose estimation for underwater robots. - Masahiro Ishida; Kazuhiro Shimonomura (SII, 2012)

Real-Time Testing Method for Multilevel Signal Interfaces and Its Impact on Test Cost. - Masahiro Ishida; Kiyotaka Ichiyama; Tasuku Fujibe; Daisuke Watanabe; Masayuki Kawabata (IEEE Des. Test Comput., 2012)

A functional test of 2-GHz/4-GHz RF digital communication device using digital tester. - Kiyotaka Ichiyama; Masahiro Ishida; Kenichi Nagatani; Toshifumi Watanabe (ITC, 2013)

An ATE Based 32 Gbaud PAM-4 At-Speed Characterization and Testing Solution. - Jose Moreira; Hubert Werkmann; Masahiro Ishida; Bernhard Roth; Volker Filsinger; Sui-Xia Yang (ATS, 2014)

30.5 A GaN 3×3 matrix converter chipset with Drive-by-Microwave technologies. - Shuichi Nagai; Yasuhiro Yamada; Noboru Negoro; Hiroyuki Handa; Yuji Kudoh; Hiroaki Ueno; Masahiro Ishida; Nobuyuki Otuska; Daisuke Ueda (ISSCC, 2014)

Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. - Masahiro Ishida; Takashi Kusaka; Toru Nakura; Satoshi Komatsu; Kunihiro Asada (ITC, 2014)

Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test. - Masahiro Ishida; Takahiro J. Yamaguchi; Mani Soma; Terri S. Fiez; Mike Peng Li (VTS, 2014)

A Technique for Analyzing On-Chip Power Supply Impedance. - Masahiro Ishida; Toru Nakura; Akira Matsukawa; Rimon Ikeno; Kunihiro Asada (ATS, 2015)

An ATE system for testing 2.4-GHz RF digital communication devices with QAM signal interfaces. - Masahiro Ishida; Kiyotaka Ichiyama (ITC, 2015)

A new method for measuring alias-free aperture jitter in an ADC output. - Takahiro J. Yamaguchi; Katsuhiko Degawa; Masayuki Kawabata; Masahiro Ishida; Koichiro Uekusa; Mani Soma (ITC, 2015)

Conducted noise of GaN Schottky barrier diode in a DC-DC converter. - Takaaki Ibuchi; Tsuyoshi Funaki; Shinji Ujita; Masahiro Ishida; Tetsuzo Ueda (IEICE Electron. Express, 2015)

An Optical Interconnection Test Method Applicable to 100-Gb/s Transceivers Using an ATE Based Hardware. - Kazuki Shirahata; Takeshi Mizushima; Tasuku Fujibe; Hidenobu Matsumura; Tomoyuki Itakura; Masahiro Ishida; Daisuke Watanabe; Shin Masuda (ATS, 2016)

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. - Toru Nakura; Naoki Terao; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (ITC, 2016)

A fully integrated GaN-based power IC including gate drivers for high-efficiency DC-DC Converters. - Shinji Ujita; Yusuke Kinoshita; Hidekazu Umeda; Tatsuo Morita; Kazuhiro Kaibara; Satoshi Tamura; Masahiro Ishida; Tetsuzo Ueda (VLSI Circuits, 2016)

An ATE System for Testing RF Digital Communication Devices With QAM Signal Interfaces. - Masahiro Ishida; Kiyotaka Ichiyama (IEEE Des. Test, 2016)

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. - Masahiro Ishida; Toru Nakura; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (J. Electron. Test., 2016)

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. - Masahiro Ishida; Toru Nakura; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (IEICE Trans. Electron., 2016)

Extension of power supply impedance emulation method on ATE for multiple power domain. - Naoki Terao; Toru Nakura; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (ETS, 2017)

A jitter separation and BER estimation method for asymmetric total jitter distributions. - Masahiro Ishida; Kiyotaka Ichiyama (ITC, 2017)

Innovative practices session 9B innovative practices in Asia-1: From quality perspective. - Kazumi Hatayama; Masahiro Ishida (VTS, 2017)

Innovative practices session 10B innovative practices in Asia-2: From cost perspective. - Kazumi Hatayama; Masahiro Ishida (VTS, 2017)

A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces. - Kiyotaka Ichiyama; Takashi Kusaka; Masahiro Ishida (ITC, 2018)

Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. - Naoki Terao; Toru Nakura; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (J. Electron. Test., 2018)

A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces. - Kiyotaka Ichiyama; Takashi Kusaka; Masahiro Ishida (ITC, 2019)

Application of Residue Sampling to RF/AMS Device Testing. - Shogo Katayama; Yudai Abe; Anna Kuwana; Koji Asami; Masahiro Ishida; Ryuya Ohta; Haruo Kobayashi 001 (ATS, 2021)