A Data Flow Computer Architecture with Program and Token Memories. - Masahiro Sowa; Tadao Murata (IEEE Trans. Computers, 1982)

A Timed Petri Net Model and Simulation of a Dataflow Computer. - T. Smigelski; Tadao Murata; Masahiro Sowa (PNPM, 1985)

A Method for Speeding up Serial Processing in Dataflow Computers by Means of a Program Counter. - Masahiro Sowa (Comput. J., 1987)

Performance of a simulated dataflow computer DFNDR-2. - Masahiro Sowa; Akitoshi Kamimura (Syst. Comput. Jpn., 1987)

High Speed Synchronization for a Statically Scheduled Superscalar Processor. - Takaya Arita; Masahiro Sowa (Int. J. High Speed Comput., 1991)

Parallel execution on the function-partitioned processor with multiple instruction streams. - Masahiro Sowa; Takaya Arita; Tadaaki Kawamura; Hiromitsu Takagi (Syst. Comput. Jpn., 1991)

Performance of the PN superscalar processor as estimated by simulation. - Takaya Arita; Hiroaki Ito; Masahiro Sowa (Syst. Comput. Jpn., 1992)

Delayed instruction execution on a long instruction word (LIW) computer. - Komei Kato; Takaya Arita; Masahiro Sowa (Syst. Comput. Jpn., 1992)

A static processor-scheduling algorithm resistive to dynamic fluctuation of execution timing. - Hiromitsu Takagi; Takaya Arita; Masahiro Sowa (Syst. Comput. Jpn., 1993)

V++: An Instruction-Restructurable Processor Architecture. - Takaya Arita; Hiromitsu Takagi; Masahiro Sowa (HICSS (1), 1994)

Hybrid Processor Based on VLIW and PN-Superscalar. - Shusuke Okamoto; Masahiro Sowa (PDPTA, 1996)

Program Controlled Cache Memory on Parallel Computer. - Mitsuaki Nakasumi; Shusuke Okamoto; Masahiro Sowa (PDPTA, 1997)

Intruction Fetch Mechanism for PN-Superscalar. - Shusuke Okamoto; Masahiro Sowa (PDPTA, 1997)

Access route control by an extended key/lock scheme. - Soichi Shigeta; Kentaro Shimizu; Masahiro Sowa (Comput. Syst. Sci. Eng., 2001)

Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing Systems. - Kirilka Nikolova; Masahiro Sowa (HPCS, 2002)

Compiler-Controlled Parallelism-Independent Scheduling for Parallel and Distributed Systems. - Kirilka Nikolova; Sou Pei You; Masahiro Sowa (PARA, 2002)

Proposal and Design of a Parallel Queue Processor Architecture (PQP). - Masahiro Sowa; Ben A. Abderazek; Soichi Shigeta; Kirilka Nikolova; Tsutomu Yoshinaga (IASTED PDCS, 2002)

On the Design of a Register Queue Based Processor Architecture (FaRM-rq). - Ben A. Abderazek; Soichi Shigeta; Tsutomu Yoshinaga; Masahiro Sowa (ISPA, 2003)

Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. - Ben A. Abderazek; Sotaro Kawata; Tsutomu Yoshinaga; Masahiro Sowa (EUC, 2005)

An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. - Md. Musfiquzzaman Akanda; Ben A. Abderazek; Sotaro Kawata; Masahiro Sowa (EUC, 2005)

Parallel Queue Processor Architecture Based on Produced Order Computation Model. - Masahiro Sowa; Ben A. Abderazek; Tsutomu Yoshinaga (J. Supercomput., 2005)

Scalable Core-Based Methodology and Synthesizable Core for Systematic Design. - Ben A. Abderazek; Tsutomu Yoshinaga; Masahiro Sowa (ICPP Workshops, 2006)

On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. - Md. Musfiquzzaman Akanda; Ben A. Abderazek; Masahiro Sowa (ISPA Workshops, 2006)

Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters. - Ta Quoc Viet; Tsutomu Yoshinaga; Ben A. Abderazek; Masahiro Sowa (Inf. Media Technol., 2006)

Design and architecture for an embedded 32-bit QueueCore. - Ben A. Abderazek; Sotaro Kawata; Masahiro Sowa (J. Embed. Comput., 2006)

High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. - Ben A. Abderazek; Tsutomu Yoshinaga; Masahiro Sowa (J. Supercomput., 2006)

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. - Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa (EUC, 2007)

Mathematical Model for Multiobjective Synthesis of NoC Architectures. - Ben A. Abderazek; Mushfiquzzaman Akanda; Tsutomu Yoshinaga; Masahiro Sowa (ICPP Workshops, 2007)

New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP. - Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa (PDCAT, 2007)

Queue Register File Optimization Algorithm for QueueCore Processor. - Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa (SBAC-PAD, 2007)

Optimizing Reaching Definitions Overhead in Queue Processors. - Yuki Nakanishi; Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa (J. Convergence Inf. Technol., 2007)

Dual-Execution Mode Processor Architecture For Embedded Applications. - Md. Musfiquzzaman Akanda; Ben A. Abderazek; Masahiro Sowa (J. Mobile Multimedia, 2007)

Quantitative Evaluation of Common Subexpression Elimination on Queue Machines. - Arquimedes Canedo; Masahiro Sowa; Ben A. Abderazek (ISPAN, 2008)

A new code generation algorithm for 2-offset producer order queue computation model. - Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa (Comput. Lang. Syst. Struct., 2008)

The QC-2 parallel Queue processor architecture. - Ben A. Abderazek; Arquimedes Canedo; Tsutomu Yoshinaga; Masahiro Sowa (J. Parallel Distributed Comput., 2008)

Dual-execution mode processor architecture. - Md. Musfiquzzaman Akanda; Ben A. Abderazek; Masahiro Sowa (J. Supercomput., 2008)

Design and implementation of a queue compiler. - Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa (Microprocess. Microsystems, 2009)

Efficient compilation for queue size constrained queue processors. - Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa (Parallel Comput., 2009)

Compiler Support for Code Size Reduction Using a Queue-Based Processor. - Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa (Trans. High Perform. Embed. Archit. Compil., 2009)

Compiling for Reduced Bit-Width Queue Processors. - Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa (J. Signal Process. Syst., 2010)

An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory. - Duc-Hung Le; Katsumi Inoue; Masahiro Sowa; Cong-Kha Pham (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)