A 32-bit Microprocessor Based on the TRON Architecture: Design of the GMICRO/100. - Tom Shimizu; Toyohiko Yoshida; Yuichi Saito; Masahito Matsuo; Tatsuya Enomoto (COMPCON, 1988)

A 32-bit microprocessor with high performance bit-map manipulation instructions. - Toru Shimizu; Shunichi Iwata; Yuichi Saito; Toyohiko Yoshida; Masahito Matsuo; Junichi Hinata; Kazunori Saito (ICCD, 1989)

A strategy for avoiding pipeline interlock delays in a microprocessor. - Toyohiko Yoshida; Masahito Matsuo; Tatsuya Ueda; Yuichi Saito (ICCD, 1990)

A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface. - Masahito Matsuo; Hiroyuki Kondo; Yukari Takata; Souichi Kobayashi; Mitsugu Satoh; Toyohiko Yoshida; Yuichi Saito; Jun-ichi Hinata (ICCD, 1994)

A dual-issue RISC processor for multimedia signal processing. - Hisakazu Sato; Edgar Holmann; Toyohiko Yoshida; Masahito Matsuo; Toru Kengaku (ICASSP, 1997)