A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit. - Katsuyuki Kaneko; Tadashi Okamoto; Masaitsu Nakajima; Yasuhiro Nakakura; Satoshi Gokita; Junji Nishikawa; Yuji Tanikawa; Hiroshi Kadota (IEEE J. Solid State Circuits, 1989)

Processing element design for a parallel computer. - Katsuyuki Kaneko; Masaitsu Nakajima; Yasuhiro Kakakura; Junji Nishikawa; Ichiro Okabayashi; Hiroshi Kadota (IEEE Micro, 1990)

Parallel computer ADENART - its architecture and application. - Hiroshi Kadota; Katsuyuki Kaneko; Ichiro Okabayashi; Tadashi Okamoto; T. Mimura; Yasuhiro Nakakura; Akiyoshi Wakatani; Masaitsu Nakajima; Junji Nishikawa; K. Zaiki; Tatsuo Nogi (ICS, 1991)

OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications. - Masaitsu Nakajima; Hiraku Nakano; Yasuhiro Nakakura; Tadahiro Yoshida; Yoshiyuki Goi; Yuji Nakai; Reiji Segawa; Takeshi Kishida; Hiroshi Kadota (ISCA, 1991)

An Accurate, High Speed Implementation of Division by the Quasi-Unity Divisor Method. - Hiraku Nakano; Masaitsu Nakajima; Yasuhiro Nakakura; Tadahiro Yoshida; Yoshiyuki Goi; Yuji Nakai; Reiji Segawa; Takeshi Kishida (IFIP Congress (1), 1992)

An 80-MFLOPS (peak) 64-b microprocessor for parallel computer. - Hiraku Nakano; Masaitsu Nakajima; Yasuhiro Nakakura; Tadahiro Yoshida; Yoshiyuki Goi; Yuji Nakai; Reiji Segawa; Takeshi Kishida; Hiroshi Kadota (IEEE J. Solid State Circuits, 1992)

Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier". - Masaitsu Nakajima; Takao Yamamoto; Masayuki Yamasaki; Tetsu Hosoki; Masaya Sumita (ASP-DAC, 2007)

Vision for future television. - Atsuki Inoue; Masaitsu Nakajima (ISSCC, 2012)

Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommittee. - Masaitsu Nakajima; Shekhar Borkar (ISSCC, 2012)