An experimental large-capacity semiconductor file memory using 16-levels/cell storage. - Masashi Horiguchi; Masakazu Aoki; Yoshinobu Nakagome; Shin'ichi Ikenaga; Katsuhiro Shimohigashi (IEEE J. Solid State Circuits, 1988)

New DRAM noise generation under half-Vcc precharge and its reduction using a transposed amplifier. - Masakazu Aoki; Shin'ichi Ikenaga; Yoshinobu Nakagome; Masashi Horiguchi; Yasushi Kawase; Yoshifumi Kawamoto; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1989)

A 1.5-V DRAM for battery-based applications. - Masakazu Aoki; Jun Etoh; Kiyoo Itoh 001; Shin Kimura; Yoshifumi Kawamoto (IEEE J. Solid State Circuits, 1989)

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier. - Masashi Horiguchi; Masakazu Aoki; Jun Etoh; Hitoshi Tanaka; Shin'ichi Ikenaga; Kiyoo Itoh 001; Kazuhiko Kajigaya; Hiroaki Kotani; Kazuyoshi Ohshima; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1990)

A flexible redundancy technique for high-density DRAMs. - Masashi Horiguchi; Jun Etoh; Masakazu Aoki; Kiyoo Itoh 001; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1991)

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. - Yoshinobu Nakagome; Kiyoo Itoh 001; Kan Takeuchi; Eiji Kume; Hitoshi Tanaka; Masanori Isoda; Tatsunori Musha; Toru Kaga; Teruaki Kisu; Takashi Nishida; Yoshifumi Kawamoto; Masakazu Aoki (IEEE J. Solid State Circuits, 1991)

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test. - Masashi Horiguchi; Masakazu Aoki; Jun Etoh; Gyoo Itoh; Kazuhiko Kajigaya; Atsushi Nozoe; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1991)

A single 1.5-V digital chip for a 106 synapse neural network. - Takao Watanabe; Katsutaka Kimura; Masakazu Aoki; Takeshi Sakata; Kiyoo Ito (IEEE Trans. Neural Networks, 1993)

Sub-1-V swing internal bus architecture for future low-power ULSIs. - Yoshinobu Nakagome; Kiyoo Itoh 001; Masanori Isoda; Kan Takeuchi; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays. - Takayuki Kawahara; Takeshi Sakata; Kiyoo Itoh 001; Yoshiki Kawajiri; Takesada Akiba; Goro Kitsukawa; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs). - Takayuki Kawahara; Masashi Horiguchi; Yoshiki Kawajiri; Goro Kitsukawa; Tokuo Kure; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

256-Mb DRAM circuit technologies for file applications. - Goro Kitsukawa; Masashi Horiguchi; Yoshiki Kawajiri; Takayuki Kawahara; Takesada Akiba; Yasushi Kawase; Toshikazu Tachibana; Takeshi Sakai; Masakazu Aoki; Syoji Shukuri; Kazuhiko Sagara; Ryo Nagai; et al. (IEEE J. Solid State Circuits, 1993)

Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. - Hitoshi Tanaka; Yoshinobu Nakagome; Jun Etoh; Eiji Yamasaki; Masakazu Aoki; Kazuyuki Miyazawa (IEEE J. Solid State Circuits, 1994)

A charge recycle refresh for Gb-scale DRAM's in file applications. - Takayulu Kawahara; Yoshiki Kawajiri; Masashi Horiguchi; Takesada Akiba; Goro Kitsukawa; Tokuo Kure; Masakazu Aoki (IEEE J. Solid State Circuits, 1994)

Subthreshold-current reduction circuits for multi-gigabit DRAM's. - Takeshi Sakata; Kiyoo Itoh 001; Masashi Horiguchi; Masakazu Aoki (IEEE J. Solid State Circuits, 1994)

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's. - Takeshi Sakata; Kiyoo Itoh 001; Masashi Horiguchi; Masakazu Aoki (IEEE J. Solid State Circuits, 1994)

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. - Takeshi Sakata; Masashi Horiguchi; Tomonori Sekiguchi; Shigeki Ueda; Hitoshi Tanaka; Eiji Yamasaki; Yoshinobu Nakagome; Masakazu Aoki; Toru Kaga; Makoto Ohkura; Ryo Nagai; Fumio Murai; et al. (IEEE J. Solid State Circuits, 1995)

Low-noise, high-speed data transmission using a ringing-canceling output buffer. - Tomonori Sekiguchi; Masashi Horiguchi; Takeshi Sakata; Yoshinobu Nakagome; Shigeki Ueda; Masakazu Aoki (IEEE J. Solid State Circuits, 1995)

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register. - Youji Idei; Katsuhiro Shimohigashi; Masakazu Aoki; Hiromasa Noda; Hidetoshi Iwai; Katsuyuki Sato; Tadashi Tachibana (IEEE J. Solid State Circuits, 1998)

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. - Hitoshi Tanaka; Masakazu Aoki; Takeshi Sakata; Shin'ichiro Kimura; Narumi Sakashita; Hideto Hidaka; Tadashi Tachibana; Katsutaka Kimura (IEEE J. Solid State Circuits, 1999)

Challenge: variability characterization and modeling for 65- to 90-nm processes. - Hiroo Masuda; Shin-ichi Ohkawa; Atsushi Kurokawa; Masakazu Aoki (CICC, 2005)

Approach for physical design in sub-100 nm era. - Hiroo Masuda; Shin-ichi Ohkawa; Masakazu Aoki (ISCAS (6), 2005)

Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip. - Masakazu Aoki; Shin-ichi Ohkawa; Hiroo Masuda (IEICE Trans. Electron., 2005)

Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis. - Masakazu Aoki; Shin-ichi Ohkawa; Hiroo Masuda (IEICE Trans. Electron., 2008)