Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture. - Hiroaki Nakata; Koji Hosogi; Masakazu Ehama; Takafumi Yuasa; Toru Fujihira; Kenichi Iwata; Motoki Kimura; Fumitaka Izuhara; Seiji Mochizuki; Masaki Nobori (ASP-DAC, 2009)

A 342mW mobile application processor with full-HD multi-standard video codec. - Kenichi Iwata; Takahiro Irita; Seiji Mochizuki; Hiroshi Ueda; Masakazu Ehama; Motoki Kimura; Jun Takemura; Keiji Matsumoto; Eiji Yamamoto; Tadashi Teranuma; Katsuji Takakubo; Hiromi Watanabe; et al. (ISSCC, 2009)

A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS. - Kenichi Iwata; Seiji Mochizuki; Motoki Kimura; Tetsuya Shibayama; Fumitaka Izuhara; Hiroshi Ueda; Koji Hosogi; Hiroaki Nakata; Masakazu Ehama; Toru Kengaku; Takuichiro Nakazawa; Hiromi Watanabe (IEEE J. Solid State Circuits, 2009)

A Full HD Multistandard Video Codec for Mobile Applications. - Motoki Kimura; Kenichi Iwata; Seiji Mochizuki; Hiroshi Ueda; Masakazu Ehama; Hiromi Watanabe (IEEE Micro, 2009)

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits. - Kenichi Iwata; Takahiro Irita; Seiji Mochizuki; Hiroshi Ueda; Masakazu Ehama; Motoki Kimura; Jun Takemura; Keiji Matsumoto; Eiji Yamamoto; Tadashi Teranuma; Katsuji Takakubo; Hiromi Watanabe; et al. (IEEE J. Solid State Circuits, 2010)

30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology. - Tsutomu Higuchi; Takuyo Kodama; Koji Kato; Ryo Fukuda; Naoya Tokiwa; Mitsuhiro Abe; Teruo Takagiwa; Yuki Shimizu; Junji Musha; Katsuaki Sakurai; Jumpei Sato; Tetsuaki Utsumi; et al. (ISSCC, 2021)