Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. - Takashi Kawanami; Masakazu Hioki; Hiroshi Nagase; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPGA, 2004)

Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity. - Takashi Kawanami; Masakazu Hioki; Hiroshi Nagase; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (IEICE Trans. Inf. Syst., 2004)

Evaluation of granularity on threshold voltage control in flex power FPGA. - Masakazu Hioki; Takashi Kawanami; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPT, 2006)

Optimal set of body bias voltages for an FPGA with field-programmable Vth components. - Takashi Kawanami; Masakazu Hioki; Yohei Matsumoto; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPT, 2006)

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. - Yohei Matsumoto; Masakazu Hioki; Takashi Kawanami; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPGA, 2007)

A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip. - Masakazu Hioki; Takashi Kawanami; Yohei Matsumoto; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike; Toshiyuki Tsutsumi (FPT, 2007)

Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA. - Takashi Kawanami; Masakazu Hioki; Yohei Matsumoto; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (IEICE Trans. Inf. Syst., 2007)

Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. - Yohei Matsumoto; Masakazu Hioki; Takashi Kawanami; Hanpei Koike; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa (ACM Trans. Reconfigurable Technol. Syst., 2008)

Fully-functional FPGA prototype with fine-grain programmable body biasing. - Masakazu Hioki; Toshihiro Sekigawa; Tadashi Nakagawa; Hanpei Koike; Yohei Matsumoto; Takashi Kawanami; Toshiyuki Tsutsumi (FPGA, 2013)

Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology. - Masakazu Hioki; Hanpei Koike (IEICE Trans. Inf. Syst., 2016)

Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device. - Toshihiro Katashita; Masakazu Hioki; Yohei Hori; Hanpei Koike (IEICE Trans. Inf. Syst., 2018)

A 2.6mW 10pTI √ Hz 33kHz Magnetoimpedance-Based Magnetometer with Automatic Loop-Gain and Bandwidth Enhancement. - Ippei Akita; Takeshi Kawano; Hitoshi Aoyama; Shunichi Tatematsu; Masakazu Hioki (ISSCC, 2022)

An Automatic Loop Gain Enhancement Technique in Magnetoimpedance-Based Magnetometer. - Ippei Akita; Takeshi Kawano; Hitoshi Aoyama; Shunichi Tatematsu; Masakazu Hioki (IEEE J. Solid State Circuits, 2022)

Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation. - Hiroshi Fuketa; Toshihiro Katashita; Yohei Hori; Masakazu Hioki (IEEE Access, 2024)

Fully Quantized Matrix Arithmetic-Only BERT Model and Its FPGA-Based Accelerator. - Hiroshi Fuketa; Toshihiro Katashita; Yohei Hori; Masakazu Hioki (IEEE Access, 2025)