A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder. - Masakazu Suzuoki; Ken Kutaragi; Toshiyuki Hiroi; Hidetaka Magoshi; Shin'ichi Okamoto; Masaaki Oka; Akio Ohba; Yasuyuki Yamamoto; Makoto Furuhashi; Masayoshi Tanaka; Teiji Yutaka; Toyoshi Okada; et al. (IEEE J. Solid State Circuits, 1999)

Designing and programming the emotion engine. - Masaaki Oka; Masakazu Suzuoki (IEEE Micro, 1999)

Importance of CAD tools and methodology in high speed CPU design: invited talk. - Haruyuki Tago; Kazuhiro Hashimoto; Nobuyuki Ikumi; Masato Nagamatsu; Masakazu Suzuoki; Yasuyuki Yamamoto (ASP-DAC, 2000)

2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing. - Nobuhiro Ide; Masashi Hirano; Yukio Endo; Shin-ichi Yoshioka; Hiroaki Murakami; Atsushi Kunimatsu; Toshinori Sato; Takayuki Kamei; Toyoshi Okada; Masakazu Suzuoki (IEEE J. Solid State Circuits, 2000)

Vector Unit Architecture for Emotion Synthesis. - Atsushi Kunimatsu; Nobuhiro Ide; Toshinori Sato; Yukio Endo; Hiroaki Murakami; Takayuki Kamei; Masashi Hirano; Fujio Ishihara; Haruyuki Tago; Masaaki Oka; Akio Ohba; Teiji Yutaka; et al. (IEEE Micro, 2000)

CPU for PlayStation 2. - Haruyuki Tago; Kazuhiro Hashimoto; Nobuyuki Ikumi; Masato Nagamatsu; Masakazu Suzuoki; Yasuyuki Yamamoto (DATE, 2001)

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. - Dac C. Pham; Erwin Behnen; Mark Bolliger; H. Peter Hofstee; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; Yoshio Masubuchi; Stephen D. Posluszny; Mack W. Riley; et al. (CICC, 2005)

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. - Dac C. Pham; Tony Aipperspach; David Boerstler; Mark Bolliger; Rajat Chaudhry; Dennis Cox; Paul E. Harvey; H. Peter Hofstee; Charles R. Johns; Jim Kahle; Atsushi Kameyama; John M. Keaty; et al. (IEEE J. Solid State Circuits, 2006)