A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. - Koichiro Minami; Muneo Fukaishi; Masayuki Mizuno; Hideaki Onishi; Kenji Noda; Kiyotaka Imai; Tadahiko Horiuchi; Hiroshi Yamaguchi; Takanori Sato; Kazuyuki Nakamura; Masakazu Yaniashina (CICC, 2001)