A 45-ns 16-Mbit DRAM with triple-well structure. - Syuso Fujii; Masaki Ogihara; Mitsuru Shimizu; Munehiro Yoshida; Kenji Numata; Takahiko Hara; Shigeyoshi Watanabe; Shizuo Sawada; Tomohisa Mizuno; Junpei Kumagai; Susumu Yoshikawa; Sejii Kaki; et al. (IEEE J. Solid State Circuits, 1989)

A 17-ns 4-Mb CMOS DRAM. - Takeshi Nagai; Kenji Numata; Masaki Ogihara; Mitsuru Shimizu; Kimimasa Imai; Takahiko Hara; Munehiro Yoshida; Yoshikazu Saito; Yoshiaki Asao; Shizuo Sawada; Syuso Fujii (IEEE J. Solid State Circuits, 1991)