On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. - Masako Fujii; Hiroaki Suzuki; Hiromi Notani; Hiroshi Makino; Hirofumi Shinohara (ESSCIRC, 2008)

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. - Masako Fujii; Koji Nii; Hiroshi Makino; Shigeki Ohbayashi; Motoshige Igarashi; Takeshi Kawamura; Miho Yokota; Nobuhiro Tsuda; Tomoaki Yoshizawa; Toshikazu Tsutsui; Naohiko Takeshita; Naofumi Murata; et al. (IEICE Trans. Electron., 2008)