An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. - Shigeyoshi Watanabe; Yukihito Oowaki; Yasuo Itoh; Koji Sakui; Kenji Numata; Tsuneaki Fuse; Takayuki Kobayashi; Kenji Tsuchida; Masahiko Chiba; Takahiko Hara; Masako Ohta; Fumio Horiguchi; et al. (IEEE J. Solid State Circuits, 1989)

New nibbled-page architecture for high-density DRAMs. - Kenji Numata; Yukihito Oowaki; Yasuo Itoh; Takahiko Hara; Kenji Tsuchida; Masako Ohta; Shigyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1989)

The stabilized reference-line (SRL) technique for scaled DRAMs. - Kenji Tsuchida; Yukihito Oowaki; Masako Ohta; Daisaburo Takashima; Shigeyoshi Watanabe; Kazuya Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

A 33-ns 64-Mb DRAM. - Yukihito Oowaki; Kenji Tsuchida; Yohji Watanabe; Daisaburo Takashima; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Akihiro Nitayama; Fumio Horiguchi; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

Word-line architecture for highly reliable 64-Mb DRAM. - Daisaburo Takashima; Yukihito Oowaki; Ryu Ogiwara; Yohji Watanabe; Kenji Tsuchida; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1992)

An experimental DRAM with a NAND-structured cell. - Takehiro Hasegawa; Daisaburo Takashima; Ryu Ogiwara; Masako Ohta; Shinichiro Shiratake; Takeshi Hamamoto; Takashi Yamada; Masami Aoki; Shigeru Ishibashi; Yukihito Oowaki; Shigeyoshi Watanabe; Fujio Masuoka (IEEE J. Solid State Circuits, 1993)

A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF). - Motoki Tokumasu; Hiroshige Fujii; Masako Ohta; Tsunealu Fuse; Atsushi Kameyama (CICC, 2002)

A 0.5-V power-supply scheme for low-power system LSIs using multi-Vth SOI CMOS technology. - Tsuneaki Fuse; Masako Ohta; Motoki Tokumasu; Hiroshige Fujii; Shigeru Kawanaka; Atsushi Kameyama (IEEE J. Solid State Circuits, 2003)