A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier. - Shouhei Kousai; Kohei Onizuka; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (ISSCC, 2012)

A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier. - Shouhei Kousai; Kohei Onizuka; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (IEEE J. Solid State Circuits, 2012)

3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier. - Shouhei Kousai; Kohei Onizuka; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (ISSCC, 2014)

Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier. - Shouhei Kousai; Kohei Onizuka; Junji Wadatsumi; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (IEEE J. Solid State Circuits, 2014)