Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. - Masami Nakajima; Michitaka Kameyama (ISMVL, 1993)

Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations. - Masami Nakajima; Michitaka Kameyama (ISMVL, 1994)

Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. - Masami Nakajima; Michitaka Kameyama (ISMVL, 1996)

A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. - Satoshi Kaneko; Hiroyuki Kondo; Norio Masui; Koichi Ishimi; Teruyuki Itou; Masayuki Satou; Naoto Okumura; Yukari Takata; Hirokazu Takata; Mamoru Sakugawa; Takashi Higuchi; Sugako Ohtani; et al. (IEEE J. Solid State Circuits, 2004)

Implementation of Face Recognition Processing Using an Embedded Processor. - Hiroyuki Kondo; Masami Nakajima; Miroslaw Bober; Krzysztof Kucharski; Osamu Yamamoto; Toru Shimizu (J. Robotics Mechatronics, 2005)

A 40GOPS 250mW massively parallel processor based on matrix architecture. - Masami Nakajima; Hideyuki Noda; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Hiroyuki Kondo; Yukihiko Shimazu; Kazutami Arimoto; Kazunori Saitoh; Toru Shimizu (ISSCC, 2006)

Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture. - Toru Shimizu; Masami Nakajima; Masahiro Kainaga (IEICE Trans. Electron., 2006)

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. - Hirokatsu Shirahama; Akira Mochizuki; Takahiro Hanyu; Masami Nakajima; Kazutami Arimoto (ISMVL, 2007)

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Masami Nakajima; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Tetsushi Tanizaki; Takayuki Gyohten; Yoshihiro Okuno; Hiroyuki Kondo; Yukihiko Shimazu; et al. (IEEE J. Solid State Circuits, 2007)

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Tetsushi Tanizaki; Takayuki Gyohten; Katsumi Dosaka; Masami Nakajima; Katsuya Mizumoto; Kanako Yoshida; Takenobu Iwao; Tetsu Nishijima; Yoshihiro Okuno; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

Heterogeneous multicore SoC for secure multimedia applications. - Hiroyuki Kondo; Masami Nakajima; Sugako Otani; Osamu Yamamoto; Norio Masui; Naoto Okumura; Mamoru Sakugawa; Masaya Kitao; Koichi Ishimi; Masayuki Sato; Fumitaka Fukuzawa; Kazuhiro Inaoka; et al. (CICC, 2008)

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. - Hiroyuki Kondo; Masami Nakajima; Norio Masui; Sugako Otani; Naoto Okumura; Yukari Takata; Takashi Nasu; Hirokazu Takata; Takashi Higuchi; Mamoru Sakugawa; Hayato Fujiwara; Kazuya Ishida; et al. (IEEE J. Solid State Circuits, 2008)

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. - Hiroyuki Kondo; Sugako Otani; Masami Nakajima; Osamu Yamamoto; Norio Masui; Naoto Okumura; Mamoru Sakugawa; Masaya Kitao; Koichi Ishimi; Masayuki Sato; Fumitaka Fukuzawa; Satoshi Imasu; et al. (IEEE J. Solid State Circuits, 2009)

A scalable massively parallel processor for real-time image processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Takayuki Gyohten; Tetsu Nishijima; Hiroyuki Yamasaki; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Yoshihiro Okuno; Tetsushi Koide; Hans Jürgen Mattausch; et al. (ISSCC, 2010)

Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G. - Yushi Moko; Yoshihiro Watanabe; Takashi Komuro; Masatoshi Ishikawa; Masami Nakajima; Kazutami Arimoto (CVPR Workshops, 2011)

A Scalable Massively Parallel Processor for Real-Time Image Processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Tetsu Nishijima; Tetsushi Tanizaki; Hiroyuki Yamasaki; Takeaki Sugimura; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Kan Murata; Kanako Yoshida; et al. (IEEE J. Solid State Circuits, 2011)

A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes. - Masami Nakajima; Ichiro Naka; Fumihiro Matsushima; Tadaaki Yamauchi (COOL Chips, 2016)