Correlation method of circuit-performance and technology fluctuations for improved design reliability. - D. Miyawaki; Shizunori Matsumoto; Hans Jürgen Mattausch; S. Ooshiro; Masami Suetake; Mitiko Miura-Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (ASP-DAC, 2001)

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. - Dondee Navarro; Takeshi Mizoguchi; Masami Suetake; Kazuya Hisamitsu; Hiroaki Ueno; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Electron., 2005)