Bit-Serial Single Flux Quantum Microprocessor CORE. - Akira Fujimaki; Masamitsu Tanaka; Takahiro Yamada; Yuki Yamanashi; Heejoung Park; Nobuyuki Yoshikawa (IEICE Trans. Electron., 2008)

Design of fast digit-serial adders using SFQ logic circuits. - Heejoung Park; Yuki Yamanashi; Nobuyuki Yoshikawa; Masamitsu Tanaka; Akira Fujimaki (IEICE Electron. Express, 2009)

Comparisons of Synchronous-Clocking SFQ Adders. - Naofumi Takagi; Masamitsu Tanaka (IEICE Trans. Electron., 2010)

Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm. - Masamitsu Tanaka; Koji Obata; Yuki Ito; Shota Takeshima; Motoki Sato; Kazuyoshi Takagi; Naofumi Takagi; Hiroyuki Akaike; Akira Fujimaki (IEICE Trans. Electron., 2010)

100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process. - Yuki Yamanashi; Toshiki Kainuma; Nobuyuki Yoshikawa; Irina Kataeva; Hiroyuki Akaike; Akira Fujimaki; Masamitsu Tanaka; Naofumi Takagi; Shuichi Nagasawa; Mutsuo Hidaka (IEICE Trans. Electron., 2010)

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits. - Kazuyoshi Takagi; Yuki Ito; Shota Takeshima; Masamitsu Tanaka; Naofumi Takagi (IEICE Trans. Electron., 2011)

Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors. - Akira Fujimaki; Masamitsu Tanaka; Ryo Kasagi; Katsumi Takagi; Masakazu Okada; Yuhi Hayakawa; Kensuke Takata; Hiroyuki Akaike; Nobuyuki Yoshikawa; Shuichi Nagasawa; Kazuyoshi Takagi; Naofumi Takagi (IEICE Trans. Electron., 2014)

High-Speed Operation of 0.25-mV RSFQ Arithmetic Logic Unit Based on 10-kA/cm2 Nb Process Technology. - Masamitsu Tanaka; Atsushi Kitayama; Masakazu Okada; Tomohito Kouketsu; Takumi Takinami; Masato Ito; Akira Fujimaki (IEICE Trans. Electron., 2014)

Single-flux-quantum cache memory architecture. - Koki Ishida; Masamitsu Tanaka; Takatsugu Ono; Koji Inoue (ISOCC, 2016)

Development of an Advanced Circuit Model for Superconducting Strip Line Detector Arrays. - Ali Bozbey; Yuma Kita; Kyohei Kamiya; Misaki Kozaka; Masamitsu Tanaka; Takekazu Ishida; Akira Fujimaki (IEICE Trans. Electron., 2016)

High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation. - Masamitsu Tanaka; Kazuyoshi Takagi; Naofumi Takagi (IEICE Trans. Electron., 2016)

Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing. - Koki Ishida; Masamitsu Tanaka; Takatsugu Ono; Koji Inoue (IEICE Trans. Electron., 2018)

Energy/Space-Efficient Rapid Single-Flux-Quantum Circuits by Using π-Shifted Josephson Junctions. - Tomohiro Kamiya; Masamitsu Tanaka; Kyosuke Sano; Akira Fujimaki (IEICE Trans. Electron., 2018)

Thermally Assisted Superconductor Transistors for Josephson-CMOS Hybrid Memories. - Kyosuke Sano; Masato Suzuki; Kohei Maruyama; Soya Taniguchi; Masamitsu Tanaka; Akira Fujimaki; Masumi Inoue; Nobuyuki Yoshikawa (IEICE Trans. Electron., 2018)

A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. - Ikki Nagaoka; Masamitsu Tanaka; Koji Inoue; Akira Fujimaki (ISSCC, 2019)

SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices. - Koki Ishida; Ilkwon Byun; Ikki Nagaoka; Kosuke Fukumitsu; Masamitsu Tanaka; Satoshi Kawakami; Teruo Tanimoto; Takatsugu Ono; Jangwoo Kim; Koji Inoue (MICRO, 2020)

32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic. - Koki Ishida; Masamitsu Tanaka; Ikki Nagaoka; Takatsugu Ono; Satoshi Kawakami; Teruo Tanimoto; Akira Fujimaki; Koji Inoue (VLSI Circuits, 2020)

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code. - Yosuke Ueno; Masaaki Kondo; Masamitsu Tanaka; Yasunari Suzuki; Yutaka Tabuchi (DAC, 2021)

Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation. - Shuichi Nagasawa; Masamitsu Tanaka; Naoki Takeuchi; Yuki Yamanashi; Shigeyuki Miyajima; Fumihiro China; Taiki Yamae; Koki Yamazaki; Yuta Somei; Naonori Sega; Yoshinao Mizugaki; Hiroaki Myoren; et al. (IEICE Trans. Electron., 2021)

Superconductor Computing for Neural Networks. - Koki Ishida; Ilkwon Byun; Ikki Nagaoka; Kosuke Fukumitsu; Masamitsu Tanaka; Satoshi Kawakami; Teruo Tanimoto; Takatsugu Ono; Jangwoo Kim; Koji Inoue (IEEE Micro, 2021)

QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery. - Yosuke Ueno; Masaaki Kondo; Masamitsu Tanaka; Yasunari Suzuki; Yutaka Tabuchi (HPCA, 2022)

XQsim: modeling cross-technology control processors for 10+K qubit quantum computers. - Ilkwon Byun; Junpyo Kim; Dongmoon Min; Ikki Nagaoka; Kosuke Fukumitsu; Iori Ishikawa; Teruo Tanimoto; Masamitsu Tanaka; Koji Inoue; Jangwoo Kim (ISCA, 2022)

Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device. - Iori Ishikawa; Ikki Nagaoka; Ryota Kashima; Koki Ishida; Kosuke Fukumitsu; Keitaro Oka; Masamitsu Tanaka; Satoshi Kawakami; Teruo Tanimoto; Takatsugu Ono; Akira Fujimaki; Koji Inoue (ISCAS, 2022)

NEO-QEC: Neural Network Enhanced Online Superconducting Decoder for Surface Codes. - Yosuke Ueno; Masaaki Kondo; Masamitsu Tanaka; Yasunari Suzuki; Yutaka Tabuchi (CoRR, 2022)

High-Frequency Operation of Low-Power Single-Flux-Quantum Circuits Fabricated Using 250 A/cm2 Nb/AlOx/Nb Planarization Process. - Masamitsu Tanaka; Yoshihiro Kitagawa; Tetsuro Satoh; Tsuyoshi Yamamoto (ICICDT, 2023)

QIsim: Architecting 10+K Qubit QC Interfaces Toward Quantum Supremacy. - Dongmoon Min; Junpyo Kim; Junhyuk Choi; Ilkwon Byun; Masamitsu Tanaka; Koji Inoue; Jangwoo Kim (ISCA, 2023)

Circuit designs for practical-scale fault-tolerant quantum computing. - Yasunari Suzuki; Yosuke Ueno; Wang Liao; Masamitsu Tanaka; Teruo Tanimoto (VLSI Technology and Circuits, 2023)

Late Breaking Results: Single Flux Quantum Based Brownian Circuits for Ultra-Law-Power Computing. - Satoshi Kawakami; Yusuke Ohtusbo; Koji Inoue; Masamitsu Tanaka (DATE, 2024)

SuperCore: An Ultra-Fast Superconducting Processor for Cryogenic Applications. - Junhyuk Choi; Ilkwon Byun; Juwon Hong; Dongmoon Min; Junpyo Kim; Jungmin Cho; Hyeonseong Jeong; Masamitsu Tanaka; Koji Inoue; Jangwoo Kim (MICRO, 2024)

Low-Power Half-Flux-Quantum based Counter Circuits for Cryogenic Quantum Computers. - Yuki Matsumoto; Teruo Tanimoto; Masamitsu Tanaka; Takatsugu Ono (QCE, 2024)

Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines. - Yosuke Ueno; Yuna Tomida; Teruo Tanimoto; Masamitsu Tanaka; Yutaka Tabuchi; Koji Inoue; Hiroshi Nakamura (IEEE Comput. Archit. Lett., 2024)

SFQ counter-based precomputation for large-scale cryogenic VQE machines. - Yosuke Ueno; Satoshi Imamura; Yuna Tomida; Teruo Tanimoto; Masamitsu Tanaka; Yutaka Tabuchi; Koji Inoue; Hiroshi Nakamura (CoRR, 2024)

C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms. - Yosuke Ueno; Satoshi Imamura; Yuna Tomida; Teruo Tanimoto; Masamitsu Tanaka; Yutaka Tabuchi; Koji Inoue; Hiroshi Nakamura (CoRR, 2024)

Approximate SFQ-Based Computing Architecture Modeling With Device-Level Guidelines. - Pratiksha Mundhe; Yuta Hano; Satoshi Kawakami; Teruo Tanimoto; Masamitsu Tanaka; Koji Inoue; Ilkwon Byun (IEEE Comput. Archit. Lett., 2025)

Ferromagnetic π Junctions on Niobium Four-Layer Structure for Superconductor Large-Scale Integrated Circuits. - Akira Fujimaki; Daiki Hasegawa; Yuto Takeshita; Feng Li; Taro Yamashita; Masamitsu Tanaka (IEICE Trans. Electron., 2025)

Demonstration of Low-Power Shift-Register Based on Half-Flux-Quantum Logic. - Masamitsu Tanaka; Toranosuke Nakayama; Shoma Tanemura; Masayuki Higashi; Feng Li; Akira Fujimaki (IEICE Trans. Electron., 2025)