Ultra-high-density interconnection technology of three-dimensional packaging. - Kenji Takahashi; Mitsuo Umemoto; Naotaka Tanaka; Kazumasa Tanida; Yoshihiko Nemoto; Yoshihiro Tomita; Masamoto Tago; Manabu Bonkohara (Microelectron. Reliab., 2003)

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2006)

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. - Kiichi Niitsu; Noriyuki Miura; Mari Inoue; Yoshihiro Nakagawa; Masamoto Tago; Masayuki Mizuno; Takayasu Sakurai; Tadahiro Kuroda (IEICE Trans. Electron., 2007)

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. - Yoichi Yoshida; Koichi Nose; Yoshihiro Nakagawa; Koichiro Noguchi; Yasuhiro Morita; Masamoto Tago; Tadahiro Kuroda; Masayuki Mizuno (ISSCC, 2009)

A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect. - Yoichiro Kurita; Koji Soejima; Katsumi Kikuchi; Masatake Takahashi; Masamoto Tago; Masahiro Koike; Koujirou Shibuya; Shintaro Yamamichi; Masaya Kawano (IEICE Trans. Electron., 2009)

An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. - Yoichi Yoshida; Koichi Nose; Yoshihiro Nakagawa; Koichiro Noguchi; Yasuhiro Morita; Masamoto Tago; Masayuki Mizuno; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2010)