A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit. - Masanao Yamaoka; Kazumasa Yanagisawa; Shoji Shukuri; Katsuhiro Norisue; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2002)

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. - Masanao Yamaoka; Kenichi Osada; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2004)

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. - Makoto Ishikawa; Tatsuya Kamei; Yuki Kondo; Masanao Yamaoka; Yasuhisa Shimazaki; Motokazu Ozawa; Saneaki Tamaki; Mikio Furuyama; Tadashi Hoshi; Fumio Arakawa; Osamu Nishii; Kenji Hirose; et al. (IEICE Trans. Electron., 2005)

A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. - Masanao Yamaoka; Yoshihiro Shinozaki; Noriaki Maeda; Yasuhisa Shimazaki; Kei Kato; Shigeru Shimada; Kazumasa Yanagisawa; Kenichi Osada (IEEE J. Solid State Circuits, 2005)

A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design. - Masanao Yamaoka; Hidetoshi Onodera (SoCC, 2006)

90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. - Masanao Yamaoka; Noriaki Maeda; Yoshihiro Shinozaki; Yasuhisa Shimazaki; Koji Nii; Shigeru Shimada; Kazumasa Yanagisawa; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors. - Masanao Yamaoka; Ryuta Tsuchiya; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

Low-voltage limitations of memory-rich nano-scale CMOS LSIs. - Kiyoo Itoh 001; Masashi Horiguchi; Masanao Yamaoka (ESSCIRC, 2007)

Operating-margin-improved SRAM with column-at-a-time body-bias control technique. - Masanao Yamaoka; Takayuki Kawahara (ESSCIRC, 2007)

Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. - Kiyoo Itoh 001; Masanao Yamaoka; Takayuki Kawahara (ACM Great Lakes Symposium on VLSI, 2007)

A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. - Masanao Yamaoka; Kenichi Osada; Takayuki Kawahara (ESSCIRC, 2008)

65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. - Masanao Yamaoka; Noriaki Maeda; Yasuhisa Shimazaki; Kenichi Osada (ISSCC, 2008)

A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. - Shigenobu Komatsu; Masanao Yamaoka; Masao Morimoto; Noriaki Maeda; Yasuhisa Shimazaki; Kenichi Osada (CICC, 2009)

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era. - Kiyoo Itoh 001; Masanao Yamaoka; Takashi Oshima (IEICE Trans. Electron., 2010)

Spatial computing architecture using randomness of memory cell stability under voltage control. - Chihiro Yoshimura; Masanao Yamaoka; Hidetaka Aoki; Hiroyuki Mizuno (ECCTD, 2013)

An energy-efficient parallel-processing method based on master-hibernating DVFS. - Masaki Hamamoto; Masanao Yamaoka (ISCAS, 2014)

An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution. - Masato Hayashi; Masanao Yamaoka; Chihiro Yoshimura; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (CANDAR, 2015)

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing. - Masanao Yamaoka; Chihiro Yoshimura; Masato Hayashi; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (ISSCC, 2015)

Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution? - N. Sugii; G. Jurczak; Masanao Yamaoka; A. Molnar; J. Tham; T. Piliszczuk; O. Nalamasu; J. Hausner; Shu Tanaka; Tadaaki Yamauchi; S. Sivaram; C. Diaz; et al. (VLSIC, 2015)

FPGA-based Annealing Processor for Ising Model. - Chihiro Yoshimura; Masato Hayashi; Takuya Okuyama; Masanao Yamaoka (CANDAR, 2016)

Computing architecture to perform approximated simulated annealing for Ising models. - Takuya Okuyama; Chihiro Yoshimura; Masato Hayashi; Masanao Yamaoka (ICRC, 2016)

Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution. - Masato Hayashi; Masanao Yamaoka; Chihiro Yoshimura; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (Int. J. Netw. Comput., 2016)

A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing. - Masanao Yamaoka; Chihiro Yoshimura; Masato Hayashi; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (IEEE J. Solid State Circuits, 2016)

An Ising Computer Based on Simulated Quantum Annealing by Path Integral Monte Carlo Method. - Takuya Okuyama; Masato Hayashi; Masanao Yamaoka (ICRC, 2017)

Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing. - Chihiro Yoshimura; Masato Hayashi; Takuya Okuyama; Masanao Yamaoka (Int. J. Netw. Comput., 2017)

FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search. - Takashi Takemoto; Normann Mertig; Masato Hayashi; Saki Susa-Tanaka; Hiroshi Teramoto; Atsuyoshi Nakamura; Ichigaku Takigawa; Shin-ichi Minato; Tamiki Komatsuzaki; Masanao Yamaoka (ReConFig, 2018)

Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity. - Yuya Sugie; Yuki Yoshida; Normann Mertig; Takashi Takemoto; Hiroshi Teramoto; Atsuyoshi Nakamura; Ichigaku Takigawa; Shin-ichi Minato; Masanao Yamaoka; Tamiki Komatsuzaki (TPNC, 2018)

An Ising model mapping to solve rectangle packing problem. - Kotaro Terada; Daisuke Oku; Sho Kanamaru; Shu Tanaka; Masato Hayashi; Masanao Yamaoka; Masao Yanagisawa; Nozomu Togawa (VLSI-DAT, 2018)

CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems. - Masanao Yamaoka; Takuya Okuyama; Masato Hayashi; Chihiro Yoshimura; Takashi Takemoto (CICC, 2019)

Efficient Ising Model Mapping to Solving Slot Placement Problem. - Sho Kanamaru; Daisuke Oku; Masashi Tawada; Shu Tanaka; Masato Hayashi; Masanao Yamaoka; Masao Yanagisawa; Nozomu Togawa (ICCE, 2019)

A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. - Takashi Takemoto; Masato Hayashi; Chihiro Yoshimura; Masanao Yamaoka (ISSCC, 2019)

A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems. - Masato Hayashi; Takashi Takemoto; Chihiro Yoshimura; Masanao Yamaoka (VLSI Circuits, 2019)

A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines. - Daisuke Oku; Kotaro Terada; Masato Hayashi; Masanao Yamaoka; Shu Tanaka; Nozomu Togawa (IEICE Trans. Inf. Syst., 2019)

CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem. - Chihiro Yoshimura; Masato Hayashi; Takashi Takemoto; Masanao Yamaoka (ASP-DAC, 2020)

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. - Kasho Yamamoto; Kota Ando; Normann Mertig; Takashi Takemoto; Masanao Yamaoka; Hiroshi Teramoto; Akira Sakai; Shinya Takamaeda-Yamazaki; Masato Motomura (ISSCC, 2020)

A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. - Takashi Takemoto; Masato Hayashi; Chihiro Yoshimura; Masanao Yamaoka (IEEE J. Solid State Circuits, 2020)

A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. - Kasho Yamamoto; Takashi Takemoto; Chihiro Yoshimura; Mayumi Mashimo; Masanao Yamaoka (A-SSCC, 2021)

4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. - Takashi Takemoto; Kasho Yamamoto; Chihiro Yoshimura; Masato Hayashi; Masafumi Tada; Hiroaki Saito; Mayumi Mashimo; Masanao Yamaoka (ISSCC, 2021)

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. - Kasho Yamamoto; Kazushi Kawamura; Kota Ando; Normann Mertig; Takashi Takemoto; Masanao Yamaoka; Hiroshi Teramoto; Akira Sakai; Shinya Takamaeda-Yamazaki; Masato Motomura (IEEE J. Solid State Circuits, 2021)

Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. - Yuya Sugie; Yuki Yoshida; Normann Mertig; Takashi Takemoto; Hiroshi Teramoto; Atsuyoshi Nakamura; Ichigaku Takigawa; Shin-ichi Minato; Masanao Yamaoka; Tamiki Komatsuzaki (Soft Comput., 2021)

Annealing Machine-assisted Learning of Graph Neural Network for Combinatorial Optimization. - Pablo Loyola; Kento Hasegawa; Andres Hoyos-Idobro; Kazuo Ono; Toyotaro Suzumura; Yu Hirate; Masanao Yamaoka (CoRR, 2025)