A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's. - Hiroyuki Yamauchi; Toshikazu Suzuki; Akihiro Sawada; Tohru Iwata; Toshiaki Tsuji; Masashi Agata; Takashi Taniguchi; Yoshinori Odake; Kazuyuki Sawada; Teruhito Ohnishi; Masanori Fukumoto; Tsutomu Fujita; et al. (IEEE J. Solid State Circuits, 1993)

A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current. - Hiroyuki Yamauchi; Tom Iwata; Akito Uno; Masanori Fukumoto; Tsutomu Fujita (IEEE J. Solid State Circuits, 1995)