Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles. - Masanori Hariyama; Michitaka Kameyama (J. Robotics Mechatronics, 1994)

Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects. - Masanori Hariyama; Yuichi Araumi; Michitaka Kameyama (J. Robotics Mechatronics, 1996)

A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. - Masanori Hariyama; Yuichi Araumi; Michitaka Kameyama (Syst. Comput. Jpn., 1997)

Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. - Masanori Hariyama; Michitaka Kameyama (ICRA, 1998)

Architecture of a high-performance stereo vision VLSI processor. - Masanori Hariyama; Seunghwan Lee; Michitaka Kameyama (Adv. Robotics, 2000)

Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture. - Masanori Hariyama; Michitaka Kameyama (J. Robotics Mechatronics, 2000)

Path Planning Based on Distance Transformation and Its VLSI Implementation. - Masanori Hariyama; Michitaka Kameyama (J. Robotics Mechatronics, 2000)

Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction. - Hideki Kazama; Masanori Hariyama; Michitaka Kameyama (J. Robotics Mechatronics, 2000)

VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. - Masanori Hariyama; Toshiki Takeuchi; Michitaka Kameyama (ICRA, 2001)

High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. - Naotaka Ohsawa; Masanori Hariyama; Michitaka Kameyama (ISVLSI, 2002)

Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. - Weisheng Chong; Masanori Hariyama; Michitaka Kameyama (ISVLSI, 2004)

Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. - Naotaka Ohsawa; Osamu Sakamoto; Masanori Hariyama; Michitaka Kameyama (ISVLSI, 2004)

Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. - Weisheng Chong; Sho Ogata; Masanori Hariyama; Michitaka Kameyama (IPDPS, 2005)

Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. - Masanori Hariyama; Weisheng Chong; Sho Ogata; Michitaka Kameyama (ISVLSI, 2005)

Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. - Weisheng Chong; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. - Masanori Hariyama; Yasuhiro Kobayashi; Haruka Sasaki; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. - Masanori Hariyama; Haruka Sasaki; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2005)

Editorial: VLSI Computing for Real-World Intelligent Systems. - Masanori Hariyama (J. Robotics Mechatronics, 2005)

Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. - Masanori Hariyama; Tetsuya Aoyama; Michitaka Kameyama (IEEE Trans. Computers, 2005)

A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. - Masanori Hariyama; Michitaka Kameyama (APCCAS, 2006)

GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. - W. H. Muthumala; Masanori Hariyama; Michitaka Kameyama (APCCAS, 2006)

Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. - Yoshihiro Nakatani; Masanori Hariyama; Michitaka Kameyama (IPDPS, 2006)

Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. - Yoshihiro Nakatani; Masanori Hariyama; Michitaka Kameyama (ISMVL, 2006)

Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. - Masanori Hariyama; Michitaka Kameyama; Yasuhiro Kobayashi (ISVLSI, 2006)

A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. - Masanori Hariyama; Sho Ogata; Michitaka Kameyama (IEICE Trans. Electron., 2006)

Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. - Masanori Hariyama; Shigeo Yamadera; Michitaka Kameyama (IEICE Trans. Electron., 2006)

Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. - Masanori Hariyama; Shota Ishihara; Noriaki Idobata; Michitaka Kameyama (ERSA, 2008)

Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (ERSA, 2008)

FPGA implementation of a vehicle detection algorithm using three-dimensional information. - Masanori Hariyama; Kensaku Yamashita; Michitaka Kameyama (IPDPS, 2008)

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. - Masanori Hariyama; Shota Ishihara; Michitaka Kameyama (IEICE Trans. Electron., 2008)

Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. - Masanori Hariyama; Naoto Yokoyama; Michitaka Kameyama (IEICE Trans. Electron., 2008)

Memory Allocation for Multi-Resolution Image Processing. - Yasuhiro Kobayashi; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2008)

Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. - Hasitha Muthumala Waidyasooriya; Weisheng Chong; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2008)

Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. - Masanori Hariyama; Keita Tanji; Michitaka Kameyama (ERSA, 2009)

A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. - Shota Ishihara; Noriaki Idobata; Masanori Hariyama; Michitaka Kameyama (ERSA, 2009)

An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. - Shota Ishihara; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (ERSA, 2009)

Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (ERSA, 2009)

Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2009)

Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. - Yasuhiro Kobayashi; Masanori Hariyama; Michitaka Kameyama (IEEE Trans. Very Large Scale Integr. Syst., 2009)

An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. - Masanori Hariyama; Ryoto Tsuchiya; Shota Ishihara; Michitaka Kameyama (ERSA, 2010)

Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (ERSA, 2010)

Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. - Hasitha Muthumala Waidyasooriya; Daisuke Okumura; Masanori Hariyama; Michitaka Kameyama (ERSA, 2010)

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. - Shota Ishihara; Noriaki Idobata; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2010)

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. - Shota Ishihara; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2010)

Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. - Hasitha Muthumala Waidyasooriya; Daisuke Okumura; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. - Yoshiya Komatsu; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (ASP-DAC, 2011)

Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. - Shota Ishihara; Ryoto Tsuchiya; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2011)

Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals? - Shota Ishihara; Noriaki Idobata; Yoshihiro Nakatani; Masanori Hariyama (J. Multiple Valued Log. Soft Comput., 2011)

Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. - Hasitha Muthumala Waidyasooriya; Yosuke Ohbayashi; Masanori Hariyama; Michitaka Kameyama (IEEE Trans. Circuits Syst. Video Technol., 2011)

A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. - Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (IEEE Trans. Very Large Scale Integr. Syst., 2011)

FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. - Hasitha Muthumala Waidyasooriya; Yasuhiro Takei; Masanori Hariyama; Michitaka Kameyama (ISCAS, 2012)

Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. - Zhengfan Xia; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (ISCAS, 2012)

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. - Yoshitaka Hiramatsu; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Tohru Nojiri; Kunio Uchiyama; Michitaka Kameyama (IEICE Trans. Electron., 2012)

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. - Hasitha Muthumala Waidyasooriya; Yosuke Ohbayashi; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2012)

Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. - Zhengfan Xia; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2012)

Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (EMBC, 2013)

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design. - Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2013)

Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators. - Yasuhiro Takei; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures. - Shota Ishihara; Noriaki Idobata; Masanori Hariyama; Michitaka Kameyama (J. Multiple Valued Log. Soft Comput., 2013)

Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing. - Hasitha Muthumala Waidyasooriya; Daisuke Ono; Masanori Hariyama; Michitaka Kameyama (APCCAS, 2014)

FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Yasuhiro Takei; Michitaka Kameyama (J. Comput. Eng., 2014)

Hardware-oriented succinct-data-structure based on block-size-constrained compression. - Hasitha Muthumala Waidyasooriya; Daisuke Ono; Masanori Hariyama (SoCPaR, 2015)

Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators. - Yasuhiro Takei; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. - Zhengfan Xia; Masanori Hariyama; Michitaka Kameyama (IEEE Trans. Very Large Scale Integr. Syst., 2015)

FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama (ICIS, 2016)

Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Kota Kasahara (ICIS, 2016)

Evaluation of an OpenCL-Based FPGA Platform for Particle Filter. - Shunsuke Tatsumi; Masanori Hariyama; Norikazu Ikoma (J. Adv. Comput. Intell. Intell. Informatics, 2016)

Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama (IEEE Trans. Parallel Distributed Syst., 2016)

Architecture of an FPGA accelerator for LDA-based inference. - Taisuke Ono; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Tsukasa Ishigaki (SNPD, 2017)

An FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Kota Kasahara (Int. J. Networked Distributed Comput., 2017)

OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions. - Hasitha Muthumala Waidyasooriya; Tsukasa Endo; Masanori Hariyama; Yasuo Ohtera (Int. J. Reconfigurable Comput., 2017)

OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology. - Hasitha Muthumala Waidyasooriya; Yasuhiro Takei; Shunsuke Tatsumi; Masanori Hariyama (IEEE Trans. Parallel Distributed Syst., 2017)

Advanced Devices and Architectures. - Masato Motomura; Masanori Hariyama; Minoru Watanabe (Principles and Structures of FPGAs, 2018)

Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. - Hasitha Muthumala Waidyasooriya; Yusuke Araki; Masanori Hariyama (ISPACS, 2018)

A System for Estimating Optimal Resected Liver Regions Considering Practical Surgical Constraints. - Yaya Watanabe; Masanori Hariyama; Mitsugi Shimoda (ISPACS, 2018)

Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems. - Yuki Hiradate; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Masaaki Harada (SCFA, 2018)

Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation. - Chia-Yin Liu; Hasitha Muthumala Waidyasooriya; Masanori Hariyama (CANDAR, 2019)

A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA. - Tomoki Shoji; Hasitha Muthumala Waidyasooriya; Taisuke Ono; Masanori Hariyama; Yuichiro Aoki; Yuki Kondoh; Yaoko Nakagawa (CANDAR Workshops, 2019)

Benchmarks for FPGA-Targeted High-Level-Synthesis. - Hasitha Muthumala Waidyasooriya; Yasuaki Iimura; Masanori Hariyama (CANDAR, 2019)

FPGA-Based Acceleration of Word2vec using OpenCL. - Taisuke Ono; Tomoki Shoji; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Yuichiro Aoki; Yuki Kondoh; Yaoko Nakagawa (ISCAS, 2019)

Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama (IEEE Access, 2019)

OpenCL-based design of an FPGA accelerator for quantum annealing simulation. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Masamichi J. Miyama; Masayuki Ohzeki (J. Supercomput., 2019)

Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories. - Chia-Yin Liu; Yi-Jung Chen; Masanori Hariyama (SAC, 2020)

A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama (IEEE Access, 2020)

An FPGA accelerator for PatchMatch multi-view stereo using OpenCL. - Shunsuke Tatsumi; Masanori Hariyama; Koichi Ito 001; Takafumi Aoki (J. Real Time Image Process., 2020)

Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama (IEEE Trans. Emerg. Top. Comput., 2021)

FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model. - Hasitha Muthumala Waidyasooriya; Yuta Ohma; Masanori Hariyama (MCSoC, 2022)

Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++. - Kosiro Obata; Hasitha Muthumala Waidyasooriya; Masanori Hariyama (MWSCAS, 2022)

OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Hiroe Iwasaki; Daisuke Kobayashi; Yuya Omori; Ken Nakamura; Koyo Nitta; Kimikazu Sano (MWSCAS, 2022)

Word2Vec FPGA Accelerator Based on Spatial and Temporal Parallelism. - Hasitha Muthumala Waidyasooriya; Shutaro Ishihara; Masanori Hariyama (PDCAT, 2022)

A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory. - Hasitha Muthumala Waidyasooriya; Hiroki Oshiyama; Yuya Kurebayashi; Masanori Hariyama; Masayuki Ohzeki (IEEE Access, 2022)

FPGA-Accelerated Searchable Encrypted Database Management Systems for Cloud Services. - Mitsuhiro Okada; Takayuki Suzuki; Naoya Nishio; Hasitha Muthumala Waidyasooriya; Masanori Hariyama (IEEE Trans. Cloud Comput., 2022)

Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators. - Chia-Yin Liu; Hasitha Muthumala Waidyasooriya; Masanori Hariyama (J. Supercomput., 2022)

Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama (J. Supercomput., 2022)

Performance evaluation of Word2vec accelerators exploiting spatial and temporal parallelism on DDR/HBM-based FPGAs. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama (J. Supercomput., 2024)

Large-Scale AGV Routing Based on Multi-FPGA SQA Acceleration. - Thinh NguyenQuang; Kosuke Matsuyama; Keisuke Shimizu; Hiroki Sugano; Eiji Kurimoto; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Masayuki Ohzeki (ASP-DAC, 2025)