120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs. - Yasushi Terada; Kazuo Kobayashi; Takeshi Nakayama; Masanori Hayashikoshi; Yoshikazu Miyawaki; Natsuo Ajika; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1989)

A high-speed parallel sensing architecture for multi-megabit flash E2PROMs. - Kiyoteru Kobayashi; Tatsuo Nakayama; Yoshikazu Miyawaki; Masanori Hayashikoshi; Yasushi Terada; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1990)

A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. - Masaki Tsukude; Kazutami Arimoto; Hideto Hidaka; Yasuhiro Konishi; Masanori Hayashikoshi; Katsunori Suma; Kazuyasu Fujishima (ITC, 1992)

A dual-mode sensing scheme of capacitor-coupled EEPROM cell. - Masanori Hayashikoshi; Hideto Hidaka; Kazutami Arimoto; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1992)

A 34-ns 16-Mb DRAM with controllable voltage down-converter. - Hideto Hidaka; Kazutami Arimoto; Kazutoshi Hirayama; Masanori Hayashikoshi; Mikio Asakura; Masaki Tsukude; Tsukasa Oishi; Shinji Kawai; Katsuhiro Suma; Yasuhiro Konishi; Koji Tanaka; Wataru Wakamiya; et al. (IEEE J. Solid State Circuits, 1992)

Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. - Masaki Tsukude; Kazutami Arimoto; Hideto Hidaka; Yasuhiro Konishi; Masanori Hayashikoshi; Katsuhiro Suma; Kazuyasu Fujishima (IEEE Des. Test Comput., 1993)

Normally-off MCU architecture for low-power sensor node. - Masanori Hayashikoshi; Yohei Sato; Hiroshi Ueki; Hiroyuki Kawai; Toru Shimizu (ASP-DAC, 2014)

Data-aware power management for periodic real-time systems with non-volatile memory. - Takashi Nakada; Takuya Shigematsu; Toshiya Komoda; Shinobu Miwa; Hiroshi Nakamura; Yohei Sato; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu (NVMSA, 2014)

Design Aid of Multi-core Embedded Systems with Energy Model. - Takashi Nakada; Kazuya Okamoto; Toshiya Komoda; Shinobu Miwa; Yohei Sato; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu; Hiroshi Nakamura (Inf. Media Technol., 2014)

Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks. - Takashi Nakada; Hiroyuki Yanagihashi; Hiroshi Ueki; Takashi Tsuchiya; Masanori Hayashikoshi; Hiroshi Nakamura (DSDIS, 2015)

Low-power multi-sensor system with normally-off sensing technology for IoT applications. - Masanori Hayashikoshi; Hideyuki Noda; Hiroyuki Kawai; Hiroyuki Kondo (ISOCC, 2016)

An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. - Takashi Nakada; Tomoki Hatanaka; Hiroshi Nakamura; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu (VLSI-SoC, 2016)

Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications. - Masanori Hayashikoshi; Hideyuki Noda; Hiroyuki Kawai; Koji Nii; Hiroyuki Kondo (COOL Chips, 2017)

Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors. - Takashi Nakada; Hiroyuki Yanagihashi; Hiroshi Nakamura; Kunimaro Imai; Hiroshi Ueki; Takashi Tsuchiya; Masanori Hayashikoshi (VLSI-SoC, 2017)

An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation. - Takashi Nakada; Tomoki Hatanaka; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu; Hiroshi Nakamura (IEICE Trans. Inf. Syst., 2017)

A Cost-Effective High Accuracy Auto-Trimming System without Tester Constraint for Low-End Embedded Flash Memory. - Junichi Suzuki; Junichi Yamashita; Masami Hanyu; Masamichi Ido; Tatsuya Saito; Yasuhiro Nakashima; Masanori Hayashikoshi; Yukiyoshi Kiyota (ISOCC, 2018)

Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications. - Masanori Hayashikoshi; Hideyuki Noda; Hiroyuki Kawai; Yasumitsu Murai; Sugako Otani; Koji Nii; Yoshio Matsuda; Hiroyuki Kondo (IEEE Trans. Multi Scale Comput. Syst., 2018)

A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. - Masanori Hayashikoshi; Hiroaki Tanizaki; Yasumitsu Murai; Takaharu Tsuji; Kiyoshi Kawabata; Koji Nii; Hideyuki Noda; Hiroyuki Kondo; Yoshio Matsuda; Hideto Hidaka (IEICE Trans. Electron., 2019)

An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors. - Takashi Nakada; Hiroyuki Yanagihashi; Kunimaro Imai; Hiroshi Ueki; Takashi Tsuchiya; Masanori Hayashikoshi; Hiroshi Nakamura (IEICE Trans. Inf. Syst., 2020)