A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS. - Takumi Danjo; Masato Yoshioka; Masayuki Isogai; Masanori Hoshino; Sanroku Tsukamoto (VLSI-DAT, 2012)

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. - Yoshiyasu Doi; Takayuki Shibasaki; Takumi Danjo; Win Chaivipas; Takushi Hashida; Hiroki Miyaoka; Masanori Hoshino; Yoichi Koyanagi; Takuji Yamamoto; Sanroku Tsukamoto; Hirotaka Tamura (ISSCC, 2013)

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. - Yoshiyasu Doi; Takayuki Shibasaki; Takumi Danjo; Win Chaivipas; Takushi Hashida; Hiroki Miyaoka; Masanori Hoshino; Yoichi Koyanagi; Takuji Yamamoto; Sanroku Tsukamoto; Hirotaka Tamura (IEEE J. Solid State Circuits, 2013)

A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS. - Takumi Danjo; Masato Yoshioka; Masayuki Isogai; Masanori Hoshino; Sanroku Tsukamoto (IEEE J. Solid State Circuits, 2014)

Decentralized Similarity Control of Composite Nondeterministic Discrete Event Systems with Local Specifications. - Masanori Hoshino; Shigemasa Takai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)