A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. - Kazumasa Suzuki; Masakazu Yamashina; Takashi Nakayama; Masanori Izumikawa; Masahiro Nomura; Hiroyuki Igura; Hideki Heiuchi; Junichi Goto; Toshiaki Inoue; Youichi Koseki; Hitoshi Abiko; Kazuhiro Okabe; et al. (IEEE J. Solid State Circuits, 1994)

A current direction sense technique for multiport SRAM's. - Masanori Izumikawa; Masakazu Yamashina (IEEE J. Solid State Circuits, 1996)

A 0.25-μm CMOS 0.9-V 100-MHz DSP core. - Masanori Izumikawa; Hiroyuki Igura; Hitoshi Wakabayashi; Ken Nakajima; Tohru Mogami; Tadahiko Horiuchi; Masakazu Yamashina (IEEE J. Solid State Circuits, 1997)