Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. - Masanori Kurimoto; Hiroaki Suzuki; Rei Akiyama; Tadao Yamanaka; Haruyuki Ohkuma; Hidehiro Takata; Hirofumi Shinohara (DAC, 2008)

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. - Hiroaki Suzuki; Masanori Kurimoto; Tadao Yamanaka; Hidehiro Takata; Hiroshi Makino; Hirofumi Shinohara (ISLPED, 2008)

Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations. - Mitsuya Fukazawa; Masanori Kurimoto; Rei Akiyama; Hidehiro Takata; Makoto Nagata (IEICE Trans. Electron., 2009)

A yield improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push rule. - Masanori Kurimoto; Jun Matsushima; Shigeki Ohbayashi; Yoshiaki Fukui (ISQED, 2010)

Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling. - Masanori Kurimoto; Hiroaki Suzuki; Rei Akiyama; Tadao Yamanaka; Haruyuki Ohkuma; Hidehiro Takata; Hirofumi Shinohara (ACM Trans. Design Autom. Electr. Syst., 2010)

System performance and energy consumption improvement methodology by delay adjustable synchronizer. - Masanori Kurimoto; Yasuhiko Takahashi; Yuji Fujiwara; Mamoru Sakugawa; Souichi Kobayashi; Hiroyuki Kondo (A-SSCC, 2011)

A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule. - Masanori Kurimoto; Jun Matsushima; Shigeki Ohbayashi; Yoshiaki Fukui; Michio Komoda; Nobuhiro Tsuda (ACM Trans. Design Autom. Electr. Syst., 2012)

Verification work reduction methodology in low-power chip implementation. - Masanori Kurimoto; Takeshi Yamamoto; Satoshi Nakano; Atsuto Hanami; Hiroyuki Kondo (ACM Trans. Design Autom. Electr. Syst., 2012)